Citra-emu/dynarmic-android
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Author SHA1 Message Date
SachinVin
a3072d68cb backend/A64/block_of_code: Always specify codeptr to run from 2020-05-23 19:55:06 +05:30
BreadFish64
018b07f186 backend/A64: fix mp 2020-05-23 19:55:06 +05:30
SachinVin
8571f06596 backend/A64: Move SP to FP in GenMemoryAccessors + Minor cleanup and 2020-05-23 19:55:06 +05:30
SachinVin
9c74e334b1 backend/A64: Use X26 for storing remaining cycles. 2020-05-23 19:55:05 +05:30
BreadFish64
b6733a089a backend/A64: add fastmem support 
fix crash on game close

fix generic exception handler

reorder hostloc gpr list

use temp register instead of X0 for writes

go back to regular std::partition
 2020-05-23 19:55:05 +05:30
BreadFish64
45a758a6f2 merge fastmem 2020-05-23 19:55:05 +05:30
SachinVin
f7fd0cff8f backend\A64\constant_pool.cpp: Correct offset calculation 2020-05-23 19:55:04 +05:30
SachinVin
c99ad2a4f3 backend/A64/a32_jitstate: Upstream changes from x64 backend 2020-05-23 19:55:04 +05:30
SachinVin
968e8cddd3 backend/A64: Add test for q flag being incorrectly set 2020-05-23 19:55:04 +05:30
SachinVin
c7f7a99428 backend/A64/a32_emit_a64.cpp: Use unused HostCall registers 2020-05-23 19:55:03 +05:30
SachinVin
79c7b026ed backend/A64/a32_emit_a64.cpp: Use MOVP2R instead of MOVI2R. 2020-05-23 19:55:03 +05:30
SachinVin
7db182a5c8 backend/A64/abi: Fix FP caller and callee save registers 2020-05-23 19:55:03 +05:30
SachinVin
a7ef959570 a64/block_of_code: use GetWritableCodePtr() instead of const_cast<...>(GetCodePtr()) 2020-05-23 19:55:03 +05:30
SachinVin
534ad728a8 backend/A64/constant_pool: Clean up unused stuff 2020-05-23 19:55:02 +05:30
SachinVin
c8ec8f8945 emit_a64_data_processing.cpp: remove pointless DoNZCV. 2020-05-23 19:55:02 +05:30
SachinVin
6f643b2352 IR + backend/*: add SetCpsrNZCVRaw and change arg1 type of SetCpsrNZCV to IR::NZCV 2020-05-23 19:55:02 +05:30
SachinVin
43d37293b1 backend/A64: Fix ASR impl 2020-05-23 19:55:01 +05:30
SachinVin
e12d635bde a64_emitter: Use Correct alias for ZR and WZR in CMP 2020-05-23 19:55:01 +05:30
SachinVin
8c66a1609e backend/A64: Use CSLE instead of branches for LSL LSR and ASR + minor cleanup 2020-05-23 19:55:01 +05:30
SachinVin
878db6d65d backend/A64: Use correct register size for EmitNot64 2020-05-23 19:55:01 +05:30
SachinVin
f8594f3bb9 tests/A32: Check if Q flag is cleared properly 2020-05-23 19:55:00 +05:30
SachinVin
296bbdd0b0 backend/A64: SignedSaturatedSub and SignedSaturatedAdd 2020-05-23 19:55:00 +05:30
SachinVin
a6c2d1952a backend/A64/emit_a64_saturation.cpp: Implement EmitSignedSaturation and EmitUnsignedSaturation 
Implements SSAT SSAT16 USAT USAT16 QASX QSAX UQASX UQSAX
 2020-05-23 19:55:00 +05:30
SachinVin
011d62d958 backend/A64: add emit_a64_saturation.cpp 2020-05-23 19:54:59 +05:30
SachinVin
ad59325b45 backend/A64: Fix EmitA32SetCpsr 2020-05-23 19:54:59 +05:30
SachinVin
61ea47ad7b backend/A64/devirtualize: remove unused DevirtualizeItanium 2020-05-23 19:54:59 +05:30
SachinVin
bb39f419e2 backend/A64: refactor to fpscr from mxcsr 2020-05-23 19:54:58 +05:30
SachinVin
47c0632e16 backend/A64: Use ScratchGpr() instead of ABI_SCRATCH1 where possible 2020-05-23 19:54:58 +05:30
SachinVin
60303dbfa8 backend/A64: support for always_little_endian 2020-05-23 19:54:58 +05:30
SachinVin
19cd6f0309 backend/a64: Add hook_hint_instructions option 
534eb0f
 2020-05-23 19:54:57 +05:30
SachinVin
3d4caa5ee1 backend /A64: cleanup 2020-05-23 19:54:57 +05:30
SachinVin
d027786e4e gitignore: add .vs dir 2020-05-23 19:54:57 +05:30
SachinVin
0c7e261aac Minor style fix 2020-05-23 19:54:57 +05:30
SachinVin
6b167a68e4 backend\A64\emit_a64_packed.cpp: Implement AddSub halving and non halving 2020-05-23 19:54:56 +05:30
SachinVin
a87b13cabf backend\A64: Instructions that got implemented on the way 2020-05-23 19:54:56 +05:30
SachinVin
17e64406aa backend\A64\emit_a64_packed.cpp: Implement Unsigned Sum of Absolute Differences 2020-05-23 19:54:55 +05:30
SachinVin
871617ac3b a64 emitter: Absolute Difference and add across vector instructions 2020-05-23 19:54:55 +05:30
SachinVin
f9ba12a9e6 backend\A64\emit_a64_packed.cpp: Implement Packed Select 2020-05-23 19:54:54 +05:30
SachinVin
607a3c7110 Backend/a64: Fix asset when falling back to interpreter 2020-05-23 19:54:54 +05:30
SachinVin
a5564f588d backend\A64\emit_a64_packed.cpp: Implement Packed Halving Add/Sub instructions 2020-05-23 19:54:53 +05:30
SachinVin
fd01d6fe0a backend\A64\emit_a64_packed.cpp: Implement Packed Saturating instructions 2020-05-23 19:54:53 +05:30
SachinVin
b4fb2569ad backend\A64\emit_a64_packed.cpp: Implement SignedPacked*- ADD and SUB 2020-05-23 19:54:52 +05:30
SachinVin
8f98852249 a64 emitter: Vector Halving and Saturation instructions 2020-05-23 19:54:52 +05:30
SachinVin
9059505a2f backend\A64\emit_a64_packed.cpp: Implement UnsignedPacked*- ADD and SUB... 
with few other in the emitter
 2020-05-23 19:54:51 +05:30
SachinVin
5ad5784ef8 a64 emitter: fix Scalar Saturating Instructions 2020-05-23 19:54:51 +05:30
SachinVin
f0eee83098 A64 Emitter: Implement Saturating Add and Sub 2020-05-23 19:54:50 +05:30
SachinVin
ebd185968d backend\A64\emit_a64_data_processing.cpp: Implement Division 2020-05-23 19:54:50 +05:30
SachinVin
def0137021 backend\A64\emit_a64_data_processing.cpp: Implement 64bit CLZ 2020-05-23 19:54:50 +05:30
SachinVin
9f227edfe4 backend\A64\emit_a64_data_processing.cpp: Implement 64bit LSL and ROR Instructions 
Also EmitTestBit
 2020-05-23 19:54:49 +05:30
SachinVin
bb70cdd28c backend\A64\emit_a64_data_processing.cpp: Implement 64bit Logical Instructions 2020-05-23 19:54:49 +05:30