MerryMage
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80fce9c4b9
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IR: Implement VectorMultiply
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2018-02-11 10:18:29 +00:00 |
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MerryMage
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a5299d0be5
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IR: Implement VectorArithmeticShiftRight
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2018-02-10 23:27:46 +00:00 |
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MerryMage
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dc9785bdcd
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IR: Implement VectorNarrow
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2018-02-10 17:01:33 +00:00 |
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MerryMage
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d9f803924e
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IR: Implement VectorSub
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2018-02-10 11:25:50 +00:00 |
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MerryMage
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e6a0a4d8ce
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IR: Implement VectorLogicalShiftRight
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2018-02-10 11:05:22 +00:00 |
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MerryMage
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670b47149e
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IR: Implement VectorZeroExtend
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2018-02-10 10:35:14 +00:00 |
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MerryMage
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7ec12cbade
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IR: Vector instructions now take esize argument in emitter
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2018-02-10 10:18:10 +00:00 |
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MerryMage
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570911e693
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IR: Implement VectorLogicalShiftLeft{8,16,32,64}
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2018-02-10 09:31:54 +00:00 |
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MerryMage
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e03a9fed98
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opcodes: Sort vector IR opcodes alphabetically
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2018-02-10 09:15:01 +00:00 |
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Lioncash
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25e7c94995
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A64: Implement ZIP1
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2018-02-07 12:06:49 +00:00 |
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FernandoS27
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c882e6819d
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Implemented UMULH and SMULH instructions
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2018-02-06 23:59:24 +00:00 |
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MerryMage
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37a9472f81
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IR: FPCompare{32,64} now return NZCV flags instead of implicitly setting them
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2018-02-05 12:26:19 +00:00 |
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Lioncash
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cd3113c208
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microinstruction: Add ConditionalSelectNZCV opcode to ReadsFromCPSR()'s switch statement
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2018-02-05 00:45:11 +00:00 |
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MerryMage
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ee8726a8ba
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IR: Add ConditionalSelectNZCV instruction
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2018-02-04 23:08:43 +00:00 |
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MerryMage
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f87ecad5a4
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A64: Implement FCVTZS (scalar, integer), FCVTZU (scalar, integer)
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2018-02-04 13:09:57 +00:00 |
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Lioncash
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ccf9493653
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A64: Implement AESD
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2018-02-03 23:11:46 +00:00 |
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Lioncash
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33bc59c55a
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A64: Implement AESE
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2018-02-03 23:11:46 +00:00 |
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MerryMage
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a7209dc2f7
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IR: Add IR instruction NZCVFromPackedFlags
This instruction expects NZCV to be in the high bits.
i.e.: The positions they were in PSTATE.
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2018-02-03 13:41:36 +00:00 |
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MerryMage
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9ea219e010
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basic_block: Fix bogus GCC maybe-uninitialized warning
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2018-02-03 03:04:44 +00:00 |
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MerryMage
|
f1d2cdde34
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fuzz_with_unicorn: Skip instructions that need to be interpreted
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2018-02-03 01:22:40 +00:00 |
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MerryMage
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2fd70e56ce
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A64: Implement FMOV (scalar, immediate)
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2018-02-03 00:52:48 +00:00 |
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MerryMage
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fcabd95ad0
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IR: Merge U32 and U64 variants of FP instructions
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2018-02-02 21:55:23 +00:00 |
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MerryMage
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6d9adb668e
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A64: Implement {ST,LD}{1,2,3,4} (multiple structures)
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2018-02-02 21:10:30 +00:00 |
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MerryMage
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cc40b83ed0
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IR: Implement VectorSetElement{8,16,32,64}
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2018-02-02 21:00:12 +00:00 |
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Lioncash
|
b608979be9
|
A64: Implement AESIMC and AESMC
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2018-02-02 17:35:16 +00:00 |
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Lioncash
|
7fb386aa1c
|
A64: Implement CRC32
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2018-01-29 17:06:17 +00:00 |
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MerryMage
|
14910e53d3
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A32: Add ExceptionRaised IR instruction and use it
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2018-01-28 12:59:52 +00:00 |
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Lioncash
|
0216cbd2a5
|
A64: Implement CRC32C
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2018-01-28 12:20:56 +00:00 |
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MerryMage
|
2e14326fd5
|
assert: Use fmt in ASSERT_MSG
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2018-01-28 00:00:58 +00:00 |
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MerryMage
|
9232be5553
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ir_opt: Add A64 Get/Set Elimination Pass
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2018-01-27 00:38:43 +00:00 |
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MerryMage
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39b7625e9d
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ir_emitter: Allow the insertion point for new instructions to be set
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2018-01-27 00:38:43 +00:00 |
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Lioncash
|
dbddb4858a
|
A64: Implement EXTR
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2018-01-26 22:07:48 +00:00 |
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MerryMage
|
0c1c82a937
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IR: Implement IR instructions A64{Get,Set}S
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2018-01-26 18:38:30 +00:00 |
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Lioncash
|
8c013e7928
|
General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
Makes namespacing a little less noisy
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2018-01-26 17:06:48 +00:00 |
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MerryMage
|
f7e8a2259a
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IR: Implement IR instructions VectorEqual{8,16,32,64,128}
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2018-01-26 01:52:06 +00:00 |
|
Fernando Sahmkow
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5ffd11d140
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A64: Implemented EOR (vector), ORR (vector, register) and ORN (vector) Instructions (#142)
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2018-01-26 00:57:56 +00:00 |
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MerryMage
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d99c99aabb
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microinstruction: Missed A64{Read,Write}Memory128 from opcode information
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2018-01-25 23:56:14 +00:00 |
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MerryMage
|
314e020992
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IR: Add IR instruction VectorZeroUpper
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2018-01-24 17:11:13 +00:00 |
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FernandoS27
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d1664096f5
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Implemented SDIV and UDIV instructions
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2018-01-24 17:09:00 +00:00 |
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MerryMage
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d6589fe3ee
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IR: Add IR instructions A64Memory{Read,Write}128
This implementation only works on macOS and Linux.
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2018-01-24 16:18:58 +00:00 |
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MerryMage
|
5421c90216
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IR: Add IR instruction VectorGetElement{8,16,32,64}
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2018-01-24 16:18:58 +00:00 |
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MerryMage
|
3932d6d695
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IR: Add IR instruction ZeroExtendToQuad
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2018-01-24 16:18:58 +00:00 |
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MerryMage
|
6f1c44e311
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IR: Implement Vector{Lower,}Broadcast{8,16,32,64}
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2018-01-24 12:01:26 +00:00 |
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Lioncash
|
cdb588dab5
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General: Default constructors and destructors where applicable
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2018-01-24 09:07:22 +00:00 |
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Lioncash
|
e300f1de46
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ir_emitter: Remove unused includes
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2018-01-24 01:50:10 +00:00 |
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MerryMage
|
ae603909d6
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ir_emitted: Remove unimplemented IR instruction Unimplemented
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2018-01-23 22:16:15 +00:00 |
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MerryMage
|
dfcbe5bd2f
|
IR: Implement Vector{Lower,}PairedAdd{8,16,32,64}
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2018-01-23 17:46:28 +00:00 |
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MerryMage
|
2b59e2ba0b
|
microinstruction: bug: Add missing opcodes
|
2018-01-23 17:46:28 +00:00 |
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Lioncash
|
768e5bcf9c
|
A64: Implement MADD and MSUB
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2018-01-23 16:08:05 +00:00 |
|
Lioncash
|
585e77d20e
|
opcodes: Add 64-bit CountLeadingZeroes opcode
|
2018-01-23 11:55:09 +00:00 |
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