Citra-emu/dynarmic-android
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253 Commits

Author SHA1 Message Date
MerryMage
f2dc9c7727 data_processing_register: Clean-up 2018-01-22 22:47:01 +00:00
MerryMage
a6d17e6bb0 A64: Implement AND (vector) 2018-01-21 18:27:06 +00:00
MerryMage
d333b5dcee A64: Implement ADD (vector, vector) 2018-01-21 17:56:27 +00:00
MerryMage
9fc1570788 IR: Simplify types. F32 -> U32, F64 -> U64, F128 -> U128 
ARM's Architecture Specification Language doesn't distinguish between floats and integers
as much as we do. This makes some things difficult to implement. Since our register
allocator is now capable of allocating values to XMMs and GPRs as necessary, the
Transfer IR instructions are no longer necessary as they used to be and they can be
removed.
 2018-01-19 01:09:46 +00:00
MerryMage
adccbf3c6b reg_alloc: Consider bitwidth of data and registers when emitting instructions 2018-01-18 13:00:16 +00:00
MerryMage
2f84137f5b IR: Implement Conditional Select 2018-01-18 11:36:52 +00:00
MerryMage
0892b487b7 A64/translate/branch: bug: Read-after-write error in BLR 2018-01-17 00:34:33 +00:00
MerryMage
a04ca20a89 ir/location_descriptor: Add missing <functional> header for std::hash 2018-01-14 20:23:24 +00:00
MerryMage
fd9530be25 A64: Optimization: Merge interpret blocks 2018-01-13 21:57:18 +00:00
MerryMage
9ab130490b A64: Add ExceptionRaised IR instruction 
The purpose of this instruction is to raise exceptions when certain decode-time
issues happen, instead of asserting at translate time. This allows us to
use the translator for code analysis without worrying about unnecessary asserts,
but also provides flexibility for the library user to perform custom behaviour
when one of these states are raised.
 2018-01-13 18:06:06 +00:00
MerryMage
7438d07f2b A64/translate: Add TranslateSingleInstruction function 2018-01-12 19:34:25 +00:00
MerryMage
16e50ca0db A32: Implement load stores (immediate) 2018-01-10 01:30:30 +00:00
MerryMage
f19f014a42 A64: Implement SVC 2018-01-09 18:57:07 +00:00
MerryMage
305456b407 A64: Implement compare and branch 2018-01-09 18:57:06 +00:00
MerryMage
08c25c9ae7 A64: PSTATE access and tests 2018-01-09 18:57:06 +00:00
MerryMage
c4abd1fda1 A64: Implement branch (register) 2018-01-09 18:57:06 +00:00
MerryMage
f3e763a667 A64: Implement logical 2018-01-09 18:57:06 +00:00
MerryMage
8a8dcad250 A64: Implement addsub instructions 2018-01-09 18:57:06 +00:00
MerryMage
1431cedcaa A64: Implement ADD_shifted 2018-01-09 18:57:06 +00:00
MerryMage
557fe60164 A64: Initial framework 2018-01-09 18:57:06 +00:00
MerryMage
512dae0361 IR: Compile-time type-checking of IR 2018-01-09 18:20:57 +00:00
MerryMage
b88b7ecbbf IR/Value: Rename RegRef and ExtRegRef to A32Reg and A32ExtReg 2018-01-09 18:20:57 +00:00
MerryMage
be094ff150 Final A32 refactor 2018-01-09 18:20:57 +00:00
MerryMage
42c83fadce IR: Split off A32 specific opcodes 2018-01-09 18:20:57 +00:00
MerryMage
f5402c8d82 A32: Split off A32 specific IREmitter 2018-01-09 18:20:57 +00:00
MerryMage
3e569047a5 Label A32 specific code appropriately 2018-01-09 18:20:57 +00:00
MerryMage
976a098bf6 jit_state: Split off CPSR.NZCV 2017-12-12 14:24:07 +00:00
MerryMage
2e6eda226c jit_state: Split off CPSR.{E,T} 
This allows us to improve code-emission for PopRSBHint. We also improve
code emission other terminals at the same time.
 2017-12-12 14:23:34 +00:00
MerryMage
4110494ac4 emit_x64: Use boost::icl::interval_map to speed up ranged invalidation 2017-12-06 20:55:29 +00:00
MerryMage
67c8e6e695 microinstruction: Remove DecrementRemainingUses 2017-11-27 20:10:23 +00:00
MerryMage
6776f83a0c basic_block: Add inst address and use count to DumpBlock 
This additional output assists with debugging.
 2017-11-27 19:51:54 +00:00
MerryMage
311b6609aa Implement IR instruction PackedSelect, reimplement SEL 2017-11-25 16:33:48 +00:00
MerryMage
c421a137c0 VCMP and VCMPE were the other way around 
- This was due to a misunderstanding of what the E in VCMPE means.
- The E refers to an exception being raised when a QNaN is encountered.
- Added unit tests for VCMP{E}
 2017-11-22 17:45:37 +00:00
MerryMage
29471be317 Standardize location of storage-class specifiers: Place at beginning of declarations 
Justification: C99 specifies that doing otherwise is an obsolescent feature.
 2017-09-29 01:23:45 +01:00
MerryMage
523ae542f4 microinstruction: Implement HasAssociatedPseudoOperation 2017-04-04 13:10:50 +01:00
MerryMage
05e97058c3 parallel: Add and Subtract with Exchange improvements 
* Remove asx argument from PackedHalvingSubAdd{U16,S16} IR instruction
* Implement Packed{Halving,}{AddSub,SubAdd}{U16,S16} IR instructions
* Implement SASX, SSAX, UASX, USAX
 2017-03-24 15:56:24 +00:00
Lynn
fd068ed6b8 Ranged cache invalidation 2017-03-20 11:58:25 +00:00
MerryMage
92a01b0cd8 Prefer ASSERT to DEBUG_ASSERT 2017-02-26 23:30:40 +00:00
MerryMage
bbeea72eba ir_opt: Remove redundant shift instructions 2017-02-26 15:28:14 +00:00
MerryMage
4ed8ee7489 microinstruction: Void arguments when invalidating instruction 2017-02-18 21:29:23 +00:00
MerryMage
642ccb0f66 ir/value: Support U16 immediates 2017-01-29 22:58:11 +00:00
MerryMage
5f7ffe0d0b microinstruction: Implement Inst::AreAllArgsImmediates 2017-01-29 22:56:59 +00:00
MerryMage
22804dc6a5 microinstruction: Arguments of Inst::Use and Inst::UndoUse should be const 2017-01-29 22:53:46 +00:00
MerryMage
1d4446cad5 microinstruction: Removed unnecessary reference from argument of Inst::ReplaceUsesWith 2017-01-29 22:52:33 +00:00
MerryMage
48693eb6ff Implement coprocessor-related microinstructions 
* CoprocInternalOperation
* CoprocSendOneWord
* CoprocSendTwoWords
* CoprocGetOneWord
* CoprocGetTwoWords
* CoprocLoadWords
* CoprocStoreWords
 2017-01-08 14:56:06 +00:00
MerryMage
d8a37e287c IR: Add IR type CoprocInfo 2017-01-08 14:56:06 +00:00
MerryMage
1efd3a764d IR: Remove unused microinstructions NegateLowWord and NegateHighWord 2017-01-05 20:16:39 +00:00
FernandoS27
d5610eb26c Implement UHASX, UHSAX, SHASX and SHSAX (#75) 2016-12-28 21:32:22 +00:00
Fernando Sahmkow
677f62dd6f Implement SHSUB8 and SHSUB16 (#74) 
* Implement IR operations PackedHalvingSubS8 and PackedHalvingSubS16
 2016-12-22 12:02:24 +00:00
MerryMage
6a269a6ebd IR: Add microinstructions UnsignedSaturation and SignedSaturation 2016-12-21 19:51:25 +00:00