backend\A64\emit_a64_floating_point.cpp: Implement VCVT instructions
This commit is contained in:
SachinVin
xperia64
parent
b61bb8e313
commit
0784f2fe0d
@ -361,7 +361,7 @@ elseif(ARCHITECTURE_Aarch64)
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# backend/A64/emit_a64_aes.cpp
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# backend/A64/emit_a64_crc32.cpp
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backend/A64/emit_a64_data_processing.cpp
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# backend/A64/emit_a64_floating_point.cpp
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backend/A64/emit_a64_floating_point.cpp
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# backend/A64/emit_a64_packed.cpp
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# backend/A64/emit_a64_saturation.cpp
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# backend/A64/emit_a64_sm4.cpp
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@ -297,4 +297,262 @@ void FPThreeOp(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, Function fn)
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ctx.reg_alloc.DefineValue(inst, result);
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}
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} // anonymous namespace
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void EmitA64::EmitFPHalfToDouble(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const ARM64Reg result = EncodeRegToSingle(ctx.reg_alloc.UseScratchFpr(args[0]));
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code.fp_emitter.FCVT(64, 16, result, result);
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ctx.reg_alloc.DefineValue(inst, result);
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}
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void EmitA64::EmitFPHalfToSingle(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const ARM64Reg result = EncodeRegToSingle(ctx.reg_alloc.UseScratchFpr(args[0]));
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code.fp_emitter.FCVT(32, 16, result, result);
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ctx.reg_alloc.DefineValue(inst, result);
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}
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void EmitA64::EmitFPSingleToDouble(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const ARM64Reg result = EncodeRegToSingle(ctx.reg_alloc.UseScratchFpr(args[0]));
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code.fp_emitter.FCVT(64, 32, result, result);
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ctx.reg_alloc.DefineValue(inst, result);
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}
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void EmitA64::EmitFPSingleToHalf(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const ARM64Reg result = EncodeRegToSingle(ctx.reg_alloc.UseScratchFpr(args[0]));
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code.fp_emitter.FCVT(16, 32, result, result);
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ctx.reg_alloc.DefineValue(inst, result);
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}
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void EmitA64::EmitFPDoubleToHalf(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const ARM64Reg result = EncodeRegToDouble(ctx.reg_alloc.UseScratchFpr(args[0]));
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code.fp_emitter.FCVT(16, 64, result, result);
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ctx.reg_alloc.DefineValue(inst, result);
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}
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void EmitA64::EmitFPDoubleToSingle(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const ARM64Reg result = EncodeRegToDouble(ctx.reg_alloc.UseScratchFpr(args[0]));
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code.fp_emitter.FCVT(32, 64, result, result);
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ctx.reg_alloc.DefineValue(inst, result);
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}
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template<size_t fsize, bool unsigned_, size_t isize>
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static void EmitFPToFixed(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const size_t fbits = args[1].GetImmediateU8();
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const auto rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
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const auto round_imm = ConvertRoundingModeToA64RoundingMode(rounding_mode);
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ASSERT_MSG(fbits == 0, "fixed point conversions are not supported yet");
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ARM64Reg src = ctx.reg_alloc.UseScratchFpr(args[0]);
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ARM64Reg result = ctx.reg_alloc.ScratchGpr();
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src = fsize == 64 ? EncodeRegToDouble(src) : EncodeRegToSingle(src);
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result = isize == 64 ? result : DecodeReg(result);
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if constexpr (unsigned_) {
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code.fp_emitter.FCVTU(result, src, round_imm);
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}
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else {
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code.fp_emitter.FCVTS(result, src, round_imm);
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}
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ctx.reg_alloc.DefineValue(inst, result);
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}
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void EmitA64::EmitFPDoubleToFixedS32(EmitContext& ctx, IR::Inst* inst) {
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EmitFPToFixed<64, false, 32>(code, ctx, inst);
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}
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void EmitA64::EmitFPDoubleToFixedS64(EmitContext& ctx, IR::Inst* inst) {
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EmitFPToFixed<64, false, 64>(code, ctx, inst);
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}
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void EmitA64::EmitFPDoubleToFixedU32(EmitContext& ctx, IR::Inst* inst) {
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EmitFPToFixed<64, true, 32>(code, ctx, inst);
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}
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void EmitA64::EmitFPDoubleToFixedU64(EmitContext& ctx, IR::Inst* inst) {
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EmitFPToFixed<64, true, 64>(code, ctx, inst);
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}
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void EmitA64::EmitFPSingleToFixedS32(EmitContext& ctx, IR::Inst* inst) {
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EmitFPToFixed<32, false, 32>(code, ctx, inst);
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}
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void EmitA64::EmitFPSingleToFixedS64(EmitContext& ctx, IR::Inst* inst) {
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EmitFPToFixed<32, false, 64>(code, ctx, inst);
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}
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void EmitA64::EmitFPSingleToFixedU32(EmitContext& ctx, IR::Inst* inst) {
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EmitFPToFixed<32, true, 32>(code, ctx, inst);
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}
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void EmitA64::EmitFPSingleToFixedU64(EmitContext& ctx, IR::Inst* inst) {
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EmitFPToFixed<32, true, 64>(code, ctx, inst);
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}
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void EmitA64::EmitFPFixedS32ToSingle(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const ARM64Reg from = DecodeReg(ctx.reg_alloc.UseGpr(args[0]));
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const ARM64Reg result = EncodeRegToSingle(ctx.reg_alloc.ScratchFpr());
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const size_t fbits = args[1].GetImmediateU8();
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const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
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ASSERT(rounding_mode == ctx.FPSCR_RMode());
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if (fbits != 0) {
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code.fp_emitter.SCVTF(result, from, fbits);
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}
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else {
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code.fp_emitter.SCVTF(result, from);
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}
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ctx.reg_alloc.DefineValue(inst, result);
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}
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void EmitA64::EmitFPFixedU32ToSingle(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const ARM64Reg from = DecodeReg(ctx.reg_alloc.UseGpr(args[0]));
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const ARM64Reg result = EncodeRegToSingle(ctx.reg_alloc.ScratchFpr());
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const size_t fbits = args[1].GetImmediateU8();
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const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
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ASSERT(rounding_mode == ctx.FPSCR_RMode());
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if (fbits != 0) {
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code.fp_emitter.UCVTF(result, from, fbits);
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}
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else {
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code.fp_emitter.UCVTF(result, from);
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}
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ctx.reg_alloc.DefineValue(inst, result);
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}
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void EmitA64::EmitFPFixedS32ToDouble(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const ARM64Reg from = DecodeReg(ctx.reg_alloc.UseGpr(args[0]));
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const ARM64Reg result = EncodeRegToDouble(ctx.reg_alloc.ScratchFpr());
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const size_t fbits = args[1].GetImmediateU8();
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const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
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ASSERT(rounding_mode == ctx.FPSCR_RMode());
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if (fbits != 0) {
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code.fp_emitter.SCVTF(result, from, fbits);
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}
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else {
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code.fp_emitter.SCVTF(result, from);
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}
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ctx.reg_alloc.DefineValue(inst, result);
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}
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void EmitA64::EmitFPFixedS64ToDouble(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const ARM64Reg from = ctx.reg_alloc.UseGpr(args[0]);
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const ARM64Reg result = EncodeRegToDouble(ctx.reg_alloc.ScratchFpr());
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const size_t fbits = args[1].GetImmediateU8();
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const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
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ASSERT(rounding_mode == ctx.FPSCR_RMode());
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if (fbits != 0) {
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code.fp_emitter.SCVTF(result, from, fbits);
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}
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else {
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code.fp_emitter.SCVTF(result, from);
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}
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ctx.reg_alloc.DefineValue(inst, result);
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}
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void EmitA64::EmitFPFixedS64ToSingle(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const ARM64Reg from = ctx.reg_alloc.UseGpr(args[0]);
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const ARM64Reg result = EncodeRegToSingle(ctx.reg_alloc.ScratchFpr());
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const size_t fbits = args[1].GetImmediateU8();
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const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
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ASSERT(rounding_mode == ctx.FPSCR_RMode());
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if (fbits != 0) {
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code.fp_emitter.SCVTF(result, from, fbits);
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}
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else {
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code.fp_emitter.SCVTF(result, from);
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}
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ctx.reg_alloc.DefineValue(inst, result);
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}
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void EmitA64::EmitFPFixedU32ToDouble(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const ARM64Reg from = DecodeReg(ctx.reg_alloc.UseGpr(args[0]));
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const ARM64Reg result = EncodeRegToDouble(ctx.reg_alloc.ScratchFpr());
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const size_t fbits = args[1].GetImmediateU8();
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const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
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ASSERT(rounding_mode == ctx.FPSCR_RMode());
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if (fbits != 0) {
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code.fp_emitter.UCVTF(result, from, fbits);
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}
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else {
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code.fp_emitter.UCVTF(result, from);
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}
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ctx.reg_alloc.DefineValue(inst, result);
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}
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void EmitA64::EmitFPFixedU64ToDouble(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const ARM64Reg from = ctx.reg_alloc.UseGpr(args[0]);
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const ARM64Reg result = EncodeRegToDouble(ctx.reg_alloc.ScratchFpr());
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const size_t fbits = args[1].GetImmediateU8();
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const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
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ASSERT(rounding_mode == ctx.FPSCR_RMode());
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if (fbits != 0) {
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code.fp_emitter.UCVTF(result, from, fbits);
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}
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else {
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code.fp_emitter.UCVTF(result, from);
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}
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ctx.reg_alloc.DefineValue(inst, result);
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}
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void EmitA64::EmitFPFixedU64ToSingle(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const ARM64Reg from = ctx.reg_alloc.UseGpr(args[0]);
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const ARM64Reg result = EncodeRegToSingle(ctx.reg_alloc.ScratchFpr());
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const size_t fbits = args[1].GetImmediateU8();
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const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
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ASSERT(rounding_mode == ctx.FPSCR_RMode());
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if (fbits != 0) {
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code.fp_emitter.UCVTF(result, from, fbits);
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}
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else {
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code.fp_emitter.UCVTF(result, from);
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}
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ctx.reg_alloc.DefineValue(inst, result);
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}
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} // namespace Dynarmic::BackendX64
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@ -515,32 +515,32 @@ OPCODE(CountLeadingZeros32, U32, U32
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//OPCODE(FPSub64, U64, U64, U64 )
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// Floating-point conversions
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//OPCODE(FPHalfToDouble, U64, U16, U8 )
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//OPCODE(FPHalfToSingle, U32, U16, U8 )
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//OPCODE(FPSingleToDouble, U64, U32, U8 )
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//OPCODE(FPSingleToHalf, U16, U32, U8 )
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//OPCODE(FPDoubleToHalf, U16, U64, U8 )
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//OPCODE(FPDoubleToSingle, U32, U64, U8 )
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//OPCODE(FPDoubleToFixedS32, U32, U64, U8, U8 )
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//OPCODE(FPDoubleToFixedS64, U64, U64, U8, U8 )
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//OPCODE(FPDoubleToFixedU32, U32, U64, U8, U8 )
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//OPCODE(FPDoubleToFixedU64, U64, U64, U8, U8 )
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OPCODE(FPHalfToDouble, U64, U16, U8 )
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OPCODE(FPHalfToSingle, U32, U16, U8 )
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OPCODE(FPSingleToDouble, U64, U32, U8 )
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OPCODE(FPSingleToHalf, U16, U32, U8 )
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OPCODE(FPDoubleToHalf, U16, U64, U8 )
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OPCODE(FPDoubleToSingle, U32, U64, U8 )
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OPCODE(FPDoubleToFixedS32, U32, U64, U8, U8 )
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OPCODE(FPDoubleToFixedS64, U64, U64, U8, U8 )
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OPCODE(FPDoubleToFixedU32, U32, U64, U8, U8 )
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OPCODE(FPDoubleToFixedU64, U64, U64, U8, U8 )
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//OPCODE(FPHalfToFixedS32, U32, U16, U8, U8 )
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//OPCODE(FPHalfToFixedS64, U64, U16, U8, U8 )
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//OPCODE(FPHalfToFixedU32, U32, U16, U8, U8 )
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//OPCODE(FPHalfToFixedU64, U64, U16, U8, U8 )
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//OPCODE(FPSingleToFixedS32, U32, U32, U8, U8 )
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//OPCODE(FPSingleToFixedS64, U64, U32, U8, U8 )
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//OPCODE(FPSingleToFixedU32, U32, U32, U8, U8 )
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//OPCODE(FPSingleToFixedU64, U64, U32, U8, U8 )
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//OPCODE(FPFixedU32ToSingle, U32, U32, U8, U8 )
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//OPCODE(FPFixedS32ToSingle, U32, U32, U8, U8 )
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//OPCODE(FPFixedU32ToDouble, U64, U32, U8, U8 )
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//OPCODE(FPFixedU64ToDouble, U64, U64, U8, U8 )
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//OPCODE(FPFixedU64ToSingle, U32, U64, U8, U8 )
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//OPCODE(FPFixedS32ToDouble, U64, U32, U8, U8 )
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//OPCODE(FPFixedS64ToDouble, U64, U64, U8, U8 )
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//OPCODE(FPFixedS64ToSingle, U32, U64, U8, U8 )
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OPCODE(FPSingleToFixedS32, U32, U32, U8, U8 )
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OPCODE(FPSingleToFixedS64, U64, U32, U8, U8 )
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OPCODE(FPSingleToFixedU32, U32, U32, U8, U8 )
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OPCODE(FPSingleToFixedU64, U64, U32, U8, U8 )
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OPCODE(FPFixedU32ToSingle, U32, U32, U8, U8 )
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OPCODE(FPFixedS32ToSingle, U32, U32, U8, U8 )
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OPCODE(FPFixedU32ToDouble, U64, U32, U8, U8 )
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OPCODE(FPFixedU64ToDouble, U64, U64, U8, U8 )
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OPCODE(FPFixedU64ToSingle, U32, U64, U8, U8 )
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OPCODE(FPFixedS32ToDouble, U64, U32, U8, U8 )
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OPCODE(FPFixedS64ToDouble, U64, U64, U8, U8 )
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OPCODE(FPFixedS64ToSingle, U32, U64, U8, U8 )
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// Floating-point vector instructions
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//OPCODE(FPVectorAbs16, U128, U128 )
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@ -26,10 +26,10 @@
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//INST(vfp_VABS, "VABS", "cccc11101D110000dddd101z11M0mmmm") // VFPv2
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//INST(vfp_VNEG, "VNEG", "cccc11101D110001dddd101z01M0mmmm") // VFPv2
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//INST(vfp_VSQRT, "VSQRT", "cccc11101D110001dddd101z11M0mmmm") // VFPv2
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//INST(vfp_VCVT_f_to_f, "VCVT (f32<->f64)", "cccc11101D110111dddd101z11M0mmmm") // VFPv2
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//INST(vfp_VCVT_to_float, "VCVT (to float)", "cccc11101D111000dddd101zs1M0mmmm") // VFPv2
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//INST(vfp_VCVT_to_u32, "VCVT (to u32)", "cccc11101D111100dddd101zr1M0mmmm") // VFPv2
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//INST(vfp_VCVT_to_s32, "VCVT (to s32)", "cccc11101D111101dddd101zr1M0mmmm") // VFPv2
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INST(vfp_VCVT_f_to_f, "VCVT (f32<->f64)", "cccc11101D110111dddd101z11M0mmmm") // VFPv2
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INST(vfp_VCVT_to_float, "VCVT (to float)", "cccc11101D111000dddd101zs1M0mmmm") // VFPv2
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INST(vfp_VCVT_to_u32, "VCVT (to u32)", "cccc11101D111100dddd101zr1M0mmmm") // VFPv2
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INST(vfp_VCVT_to_s32, "VCVT (to s32)", "cccc11101D111101dddd101zr1M0mmmm") // VFPv2
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//INST(vfp_VCMP, "VCMP", "cccc11101D110100dddd101zE1M0mmmm") // VFPv2
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//INST(vfp_VCMP_zero, "VCMP (with zero)", "cccc11101D110101dddd101zE1000000") // VFPv2
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