# This is a combination of 4 commits.
^ This is the 1st commit message: backend/A64: impl EmitA32SetCpsrNZ(C) + GetCFlagFromNZCV Fix NZC Stuff impl GetCFlagFromNZCV fix EmitA32SetCpsrNZC simplify EmitGetCFlagFromNZCV EmitGetNZCVFromOp clang-format clang format ^ This is the commit message #2: fix EmitA32SetCpsrNZC # This is the commit message #3: simplify EmitGetCFlagFromNZCV # This is the commit message #4: EmitGetNZCVFromOp clang-format
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SachinVin
parent
40db85e783
commit
0dde1d1ff3
@ -504,7 +504,49 @@ void A32EmitA64::EmitA32SetCpsrNZCVQ(A32EmitContext& ctx, IR::Inst* inst) {
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code._MSR(FIELD_FPSR, host_fpsr);
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}
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void A32EmitA64::EmitA32SetCpsrNZ(A32EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const ARM64Reg nz = EncodeRegTo32(ctx.reg_alloc.UseGpr(args[0]));
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const ARM64Reg nzcv = EncodeRegTo32(ctx.reg_alloc.ScratchGpr());
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code.LDR(INDEX_UNSIGNED, nzcv, X28, offsetof(A32JitState, cpsr_nzcv));
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code.ANDI2R(nzcv, nzcv, 0x3000'0000);
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code.ORR(nzcv, nzcv, nz);
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code.STR(INDEX_UNSIGNED, nzcv, X28, offsetof(A32JitState, cpsr_nzcv));
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}
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void A32EmitA64::EmitA32SetCpsrNZC(A32EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const ARM64Reg nzcv = EncodeRegTo32(ctx.reg_alloc.ScratchGpr());
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code.LDR(INDEX_UNSIGNED, nzcv, X28, offsetof(A32JitState, cpsr_nzcv));
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code.ANDI2R(nzcv, nzcv, 0x1000'0000);
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if (args[0].IsImmediate()) {
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if (args[1].IsImmediate()) {
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const u32 c = (args[1].GetImmediateU32() << 29);
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if (c) {
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code.ORRI2R(nzcv, nzcv, c);
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}
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} else {
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const ARM64Reg c = EncodeRegTo32(ctx.reg_alloc.UseGpr(args[1]));
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code.ORR(nzcv, nzcv, c, {nzcv, ST_LSL, 29});
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}
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} else {
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const ARM64Reg nz = EncodeRegTo32(ctx.reg_alloc.UseScratchGpr(args[0]));
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if (args[1].IsImmediate()) {
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const u32 c = args[1].GetImmediateU32() << 29;
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code.ORR(nzcv, nzcv, nz);
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if (c) {
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code.ORRI2R(nzcv, nzcv, c);
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}
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} else {
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const ARM64Reg c = EncodeRegTo32(ctx.reg_alloc.UseGpr(args[1]));
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code.ORR(nzcv, nzcv, nz);
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code.ORR(nzcv, nzcv, c, {nzcv, ST_LSL, 29});
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}
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}
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code.STR(INDEX_UNSIGNED, nzcv, X28, offsetof(A32JitState, cpsr_nzcv));
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}
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void A32EmitA64::EmitA32SetCheckBit(A32EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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@ -1409,8 +1451,8 @@ void A32EmitA64::EmitTerminalImpl(IR::Term::LinkBlock terminal, IR::LocationDesc
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PushRSBHelper(X1, X2, terminal.next);
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code.ForceReturnFromRunCode();
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//Todo: find a better/generic place to FlushIcache when switching between
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// far code and near code
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// Todo: find a better/generic place to FlushIcache when switching between
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// far code and near code
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code.FlushIcache();
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code.SwitchToNearCode();
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}
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@ -1551,7 +1593,9 @@ void A32EmitA64::Unpatch(const IR::LocationDescriptor& location) {
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EmitA64::Unpatch(location);
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if (config.HasOptimization(OptimizationFlag::FastDispatch)) {
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code.DisableWriting();
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SCOPE_EXIT { code.EnableWriting(); };
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SCOPE_EXIT {
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code.EnableWriting();
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};
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(*fast_dispatch_table_lookup)(location.Value()) = {};
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}
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@ -151,7 +151,7 @@ private:
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IR::Block ir_block = A32::Translate(A32::LocationDescriptor{descriptor}, config.callbacks, {config.arch_version, config.define_unpredictable_behaviour, config.hook_hint_instructions});
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Optimization::PolyfillPass(ir_block, polyfill_options);
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if (config.HasOptimization(OptimizationFlag::GetSetElimination)) {
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Optimization::A32GetSetElimination(ir_block);
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Optimization::A32GetSetElimination(ir_block, {.convert_nz_to_nzc = true});
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Optimization::DeadCodeElimination(ir_block);
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}
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if (config.HasOptimization(OptimizationFlag::ConstProp)) {
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@ -116,16 +116,80 @@ void EmitA64::EmitGetLowerFromOp(EmitContext&, IR::Inst*) {
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ASSERT_FALSE("should never happen");
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}
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void EmitA64::EmitGetNZFromOp(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const auto sign_extend = [&](ARM64Reg value) {
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switch (args[0].GetType()) {
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case IR::Type::U8:
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code.SXTB(Arm64Gen::EncodeRegTo64(value), Arm64Gen::EncodeRegTo32(value));
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break;
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case IR::Type::U16:
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code.SXTH(Arm64Gen::EncodeRegTo64(value), Arm64Gen::EncodeRegTo32(value));
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break;
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case IR::Type::U32:
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code.SXTW(Arm64Gen::EncodeRegTo64(value), Arm64Gen::EncodeRegTo32(value));
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break;
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case IR::Type::U64:
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break;
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default:
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UNREACHABLE();
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}
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};
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const Arm64Gen::ARM64Reg nz = ctx.reg_alloc.ScratchGpr();
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const Arm64Gen::ARM64Reg value = ctx.reg_alloc.UseGpr(args[0]);
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sign_extend(value);
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code.CMP(value, ZR);
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code.MRS(nz, FIELD_NZCV);
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code.ANDI2R(nz, nz, 0xC0000000);
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ctx.reg_alloc.DefineValue(inst, nz);
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}
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void EmitA64::EmitGetNZCVFromOp(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const auto sign_extend = [&](ARM64Reg value) {
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switch (args[0].GetType()) {
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case IR::Type::U8:
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code.SXTB(Arm64Gen::EncodeRegTo64(value), Arm64Gen::EncodeRegTo32(value));
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break;
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case IR::Type::U16:
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code.SXTH(Arm64Gen::EncodeRegTo64(value), Arm64Gen::EncodeRegTo32(value));
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break;
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case IR::Type::U32:
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code.SXTW(Arm64Gen::EncodeRegTo64(value), Arm64Gen::EncodeRegTo32(value));
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break;
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case IR::Type::U64:
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return;
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default:
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UNREACHABLE();
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}
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};
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Arm64Gen::ARM64Reg nzcv = ctx.reg_alloc.ScratchGpr();
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Arm64Gen::ARM64Reg value = ctx.reg_alloc.UseGpr(args[0]);
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sign_extend(value);
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code.CMP(value, ZR);
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code.MRS(nzcv, FIELD_NZCV);
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ctx.reg_alloc.DefineValue(inst, nzcv);
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}
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void EmitA64::EmitGetCFlagFromNZCV(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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if (args[0].IsImmediate()) {
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const ARM64Reg result = EncodeRegTo32(ctx.reg_alloc.ScratchGpr());
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const u32 value = (args[0].GetImmediateU32() >> 29) & 1;
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code.MOVI2R(result, value);
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ctx.reg_alloc.DefineValue(inst, result);
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} else {
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const ARM64Reg result = EncodeRegTo32(ctx.reg_alloc.UseScratchGpr(args[0]));
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code.UBFX(result, result, 29, 1);
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ctx.reg_alloc.DefineValue(inst, result);
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}
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}
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void EmitA64::EmitNZCVFromPackedFlags(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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@ -20,6 +20,8 @@ A32OPC(SetExtendedRegister64, Void, A32E
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A32OPC(GetCpsr, U32, )
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A32OPC(SetCpsr, Void, U32 )
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A32OPC(SetCpsrNZCV, Void, NZCV )
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A32OPC(SetCpsrNZ, Void, NZCV )
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A32OPC(SetCpsrNZC, Void, NZCV, U1 )
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A32OPC(SetCpsrNZCVRaw, Void, U32 )
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A32OPC(SetCpsrNZCVQ, Void, U32 )
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A32OPC(GetCFlag, U1, )
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@ -86,9 +88,10 @@ OPCODE(GetCarryFromOp, U1, Opaq
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OPCODE(GetOverflowFromOp, U1, Opaque )
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OPCODE(GetGEFromOp, U32, Opaque )
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OPCODE(GetNZCVFromOp, NZCV, Opaque )
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OPCODE(GetNZFromOp, NZCV, Opaque )
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OPCODE(GetUpperFromOp, U128, Opaque )
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OPCODE(GetLowerFromOp, U128, Opaque )
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OPCODE(GetCFlagFromNZCV, U1, NZCV )
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OPCODE(NZCVFromPackedFlags, NZCV, U32 )
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// Calculations
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