A64 Emitter: Implement Saturating Add and Sub
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@ -1992,6 +1992,17 @@ void ARM64FloatEmitter::EmitThreeSame(bool U, u32 size, u32 opcode, ARM64Reg Rd,
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(opcode << 11) | (1 << 10) | (Rn << 5) | Rd);
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}
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void ARM64FloatEmitter::EmitScalarThreeSame(bool U, u32 size, u32 opcode, ARM64Reg Rd, ARM64Reg Rn,
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ARM64Reg Rm) {
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ASSERT_MSG(!IsQuad(Rd), "%s doesn't support quads!", __func__);
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Rd = DecodeReg(Rd);
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Rn = DecodeReg(Rn);
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Rm = DecodeReg(Rm);
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Write32((U << 29) | (0b1011110001 << 21) | (size << 22) | (Rm << 16) |
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(opcode << 11) | (1 << 10) | (Rn << 5) | Rd);
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}
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void ARM64FloatEmitter::EmitCopy(bool Q, u32 op, u32 imm5, u32 imm4, ARM64Reg Rd, ARM64Reg Rn) {
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Rd = DecodeReg(Rd);
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Rn = DecodeReg(Rn);
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@ -2787,6 +2798,20 @@ void ARM64FloatEmitter::EmitScalar3Source(bool isDouble, ARM64Reg Rd, ARM64Reg R
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(Ra << 10) | (Rn << 5) | Rd);
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}
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// Scalar three same
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void ARM64FloatEmitter::SQADD(ESize esize, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm) {
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EmitScalarThreeSame(0, static_cast<u32>(esize), 0b000011, Rd, Rn, Rm);
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}
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void ARM64FloatEmitter::SQSUB(ESize esize, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm) {
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EmitScalarThreeSame(0, static_cast<u32>(esize), 0b001011, Rd, Rn, Rm);
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}
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void ARM64FloatEmitter::UQADD(ESize esize, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm) {
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EmitScalarThreeSame(1, static_cast<u32>(esize), 0b000011, Rd, Rn, Rm);
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}
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void ARM64FloatEmitter::UQSUB(ESize esize, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm) {
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EmitScalarThreeSame(1, static_cast<u32>(esize), 0b001011, Rd, Rn, Rm);
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}
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// Scalar floating point immediate
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void ARM64FloatEmitter::FMOV(ARM64Reg Rd, uint8_t imm8) {
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EmitScalarImm(0, 0, 0, 0, Rd, imm8);
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@ -295,6 +295,14 @@ enum RoundingMode {
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ROUND_Z, // round towards zero
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};
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// Size of each element in the Vector
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enum ESize {
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B, // Byte
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H, // Half Word
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S, // Single Word
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D, // Double Word
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};
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struct FixupBranch {
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u8* ptr;
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// Type defines
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@ -945,6 +953,12 @@ public:
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void FNMADD(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ARM64Reg Ra);
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void FNMSUB(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ARM64Reg Ra);
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// Scalar three same
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void SQADD(ESize esize, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void UQADD(ESize esize, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void SQSUB(ESize esize, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void UQSUB(ESize esize, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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// Scalar floating point immediate
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void FMOV(ARM64Reg Rd, uint8_t imm8);
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