Citra-emu/dynarmic
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

backend/A64: Implement AndNot32

Browse Source 
fix AndNot32
This commit is contained in:
SachinVin 2022-09-10 13:53:05 +05:30
parent ef03b3f16c
commit 40db85e783
2 changed files with 10 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
src/dynarmic/backend/A64/emit_a64_data_processing.cpp
View File

@ -911,6 +911,15 @@ void EmitA64::EmitAnd64(EmitContext& ctx, IR::Inst* inst) {
ctx.reg_alloc.DefineValue(inst, result); ctx.reg_alloc.DefineValue(inst, result);
} }
void EmitA64::EmitAndNot32(EmitContext& ctx, IR::Inst* inst) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
Arm64Gen::ARM64Reg op_a = EncodeRegTo32(ctx.reg_alloc.UseGpr(args[0]));
Arm64Gen::ARM64Reg result = EncodeRegTo32(ctx.reg_alloc.UseScratchGpr(args[1]));
code.BIC(result, op_a, result);
ctx.reg_alloc.DefineValue(inst, result);
}
void EmitA64::EmitEor32(EmitContext& ctx, IR::Inst* inst) { void EmitA64::EmitEor32(EmitContext& ctx, IR::Inst* inst) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst); auto args = ctx.reg_alloc.GetArgumentInfo(inst);

2
src/dynarmic/backend/A64/opcodes.inc
View File

@ -136,7 +136,7 @@ OPCODE(SignedDiv32, U32, U32,
OPCODE(SignedDiv64, U64, U64, U64 ) OPCODE(SignedDiv64, U64, U64, U64 )
OPCODE(And32, U32, U32, U32 ) OPCODE(And32, U32, U32, U32 )
OPCODE(And64, U64, U64, U64 ) OPCODE(And64, U64, U64, U64 )
//OPCODE(AndNot32, U32, U32, U32 ) OPCODE(AndNot32, U32, U32, U32 )
//OPCODE(AndNot64, U64, U64, U64 ) //OPCODE(AndNot64, U64, U64, U64 )
OPCODE(Eor32, U32, U32, U32 ) OPCODE(Eor32, U32, U32, U32 )
OPCODE(Eor64, U64, U64, U64 ) OPCODE(Eor64, U64, U64, U64 )