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frontend/ir_emitter: Add half-precision opcode for FPVectorRecipEstimate

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This commit is contained in:
Lioncash 2019-04-13 19:02:26 -04:00
parent 1615ba0adc
commit c55db96819
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GPG Key ID: 4E3C3CC1031BA9C7
4 changed files with 8 additions and 0 deletions
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4
src/backend/x64/emit_x64_vector_floating_point.cpp
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@ -1092,6 +1092,10 @@ static void EmitRecipEstimate(BlockOfCode& code, EmitContext& ctx, IR::Inst* ins
});
}
void EmitX64::EmitFPVectorRecipEstimate16(EmitContext& ctx, IR::Inst* inst) {
EmitRecipEstimate<u16>(code, ctx, inst);
}
void EmitX64::EmitFPVectorRecipEstimate32(EmitContext& ctx, IR::Inst* inst) {
EmitRecipEstimate<u32>(code, ctx, inst);
}

2
src/frontend/ir/ir_emitter.cpp
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@ -2273,6 +2273,8 @@ U128 IREmitter::FPVectorPairedAddLower(size_t esize, const U128& a, const U128&
U128 IREmitter::FPVectorRecipEstimate(size_t esize, const U128& a) {
switch (esize) {
case 16:
return Inst<U128>(Opcode::FPVectorRecipEstimate16, a);
case 32:
return Inst<U128>(Opcode::FPVectorRecipEstimate32, a);
case 64:

1
src/frontend/ir/microinstruction.cpp
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@ -337,6 +337,7 @@ bool Inst::ReadsFromAndWritesToFPSRCumulativeExceptionBits() const {
case Opcode::FPVectorPairedAddLower64:
case Opcode::FPVectorPairedAdd32:
case Opcode::FPVectorPairedAdd64:
case Opcode::FPVectorRecipEstimate16:
case Opcode::FPVectorRecipEstimate32:
case Opcode::FPVectorRecipEstimate64:
case Opcode::FPVectorRecipStepFused16:

1
src/frontend/ir/opcodes.inc
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@ -572,6 +572,7 @@ OPCODE(FPVectorPairedAdd32, U128, U128
OPCODE(FPVectorPairedAdd64, U128, U128, U128 )
OPCODE(FPVectorPairedAddLower32, U128, U128, U128 )
OPCODE(FPVectorPairedAddLower64, U128, U128, U128 )
OPCODE(FPVectorRecipEstimate16, U128, U128 )
OPCODE(FPVectorRecipEstimate32, U128, U128 )
OPCODE(FPVectorRecipEstimate64, U128, U128 )
OPCODE(FPVectorRecipStepFused16, U128, U128, U128 )