MerryMage
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06bea0ceaa
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A64: Implement CMEQ (register, vector)
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2018-01-26 01:52:42 +00:00 |
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MerryMage
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f7e8a2259a
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IR: Implement IR instructions VectorEqual{8,16,32,64,128}
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2018-01-26 01:52:06 +00:00 |
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MerryMage
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f833a17906
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reg_alloc: Use std::exchange
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2018-01-26 01:51:04 +00:00 |
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Fernando Sahmkow
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5ffd11d140
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A64: Implemented EOR (vector), ORR (vector, register) and ORN (vector) Instructions (#142)
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2018-01-26 00:57:56 +00:00 |
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Lioncash
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fc82109071
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unicorn_load: Minor Windows-related changes
- Add missing include
- Fix a potential compilation issue where the constructor wouldn't be able to execute, as it would be private.
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2018-01-26 00:52:46 +00:00 |
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MerryMage
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d08b738662
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tests/A64: Test memory writes
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2018-01-25 23:56:57 +00:00 |
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MerryMage
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d99c99aabb
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microinstruction: Missed A64{Read,Write}Memory128 from opcode information
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2018-01-25 23:56:14 +00:00 |
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MerryMage
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85034beaac
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emit_x64_packed: EmitPackedSubU16 modified xmm_b wasn't writeable
For CPUs that didn't support SSE4.1, this was a bug.
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2018-01-25 18:41:53 +00:00 |
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Lioncash
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1ffe4e03d9
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tests: Fix truncation in GetFpcr()
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2018-01-25 18:26:32 +00:00 |
|
James Rowe
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0cc1bce1a8
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Fixup: Xn|SP are 64 bit addresses encoded in the Rn field
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2018-01-25 17:46:14 +00:00 |
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James Rowe
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76aaa84687
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A64: Fix bugs and address review comments
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2018-01-25 17:46:14 +00:00 |
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James Rowe
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7825ae3a4f
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Add missing returns
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2018-01-25 17:46:14 +00:00 |
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James Rowe
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ddb5b3469d
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A64: Implement Load/Store register (unprivileged)
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2018-01-25 17:46:14 +00:00 |
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MerryMage
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7f3a790de5
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fixup: travis: Test with disabled CPU feature detection
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2018-01-24 19:42:54 +00:00 |
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Lioncash
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850337e434
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CMakeLists: Add opcodes.inc to the source file list
Allows the file to show up nicely within IDEs
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2018-01-24 19:42:02 +00:00 |
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MerryMage
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7d389fb5f8
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travis: Test with disabled CPU feature detection
Ensure that fallbacks are working correctly.
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2018-01-24 19:22:45 +00:00 |
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MerryMage
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314e020992
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IR: Add IR instruction VectorZeroUpper
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2018-01-24 17:11:13 +00:00 |
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MerryMage
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8ce3e0518a
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a64_emit_x64: bug: EmitA64WriteMemory128 should write not read
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2018-01-24 17:10:44 +00:00 |
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FernandoS27
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d1664096f5
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Implemented SDIV and UDIV instructions
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2018-01-24 17:09:00 +00:00 |
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MerryMage
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8873d17db2
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A64: Implement LDR/STR (immediate, SIMD&FP)
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2018-01-24 16:28:18 +00:00 |
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MerryMage
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7f5ce36368
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IR: Add IR instructions A64Memory{Read,Write}128
Add the Windows ABI implementation
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2018-01-24 16:28:18 +00:00 |
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MerryMage
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d6589fe3ee
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IR: Add IR instructions A64Memory{Read,Write}128
This implementation only works on macOS and Linux.
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2018-01-24 16:18:58 +00:00 |
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MerryMage
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5421c90216
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IR: Add IR instruction VectorGetElement{8,16,32,64}
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2018-01-24 16:18:58 +00:00 |
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MerryMage
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3932d6d695
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IR: Add IR instruction ZeroExtendToQuad
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2018-01-24 16:18:58 +00:00 |
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MerryMage
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264c446e54
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block_of_code: Add ABI_RETURN2
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2018-01-24 16:18:58 +00:00 |
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MerryMage
|
ed63cc7ae9
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interface: Move Vector typedef to config.h
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2018-01-24 16:18:58 +00:00 |
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MerryMage
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ef81c2bcfc
|
bit_util: bug: Infinite loop in HighestSetBit
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2018-01-24 16:18:58 +00:00 |
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MerryMage
|
1db423b2ad
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A64: Implement DUP (general)
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2018-01-24 12:01:26 +00:00 |
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MerryMage
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6f1c44e311
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IR: Implement Vector{Lower,}Broadcast{8,16,32,64}
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2018-01-24 12:01:26 +00:00 |
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Lioncash
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cdb588dab5
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General: Default constructors and destructors where applicable
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2018-01-24 09:07:22 +00:00 |
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Lioncash
|
e300f1de46
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ir_emitter: Remove unused includes
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2018-01-24 01:50:10 +00:00 |
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Lioncash
|
0e5988258d
|
A64: Implement RBIT
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2018-01-24 01:49:58 +00:00 |
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MerryMage
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ae603909d6
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ir_emitted: Remove unimplemented IR instruction Unimplemented
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2018-01-23 22:16:15 +00:00 |
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MerryMage
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f014a5bec7
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emit_x64: Extract BlockRangeInformation, remove template parameter
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2018-01-23 19:44:35 +00:00 |
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MerryMage
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5f5e664a66
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emit_x64: Use JitStateInfo
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2018-01-23 19:44:35 +00:00 |
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MerryMage
|
d52cb2d0de
|
A64: Implement CLS
This is not the cleanest implementation.
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2018-01-23 19:44:35 +00:00 |
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MerryMage
|
24383e543b
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A64: Implement ADDP (vector)
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2018-01-23 17:46:28 +00:00 |
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MerryMage
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dfcbe5bd2f
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IR: Implement Vector{Lower,}PairedAdd{8,16,32,64}
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2018-01-23 17:46:28 +00:00 |
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MerryMage
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961e64dfaf
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backend_x64: Split emit_x64
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2018-01-23 17:46:28 +00:00 |
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MerryMage
|
41d9a6421d
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fuzz_with_unicorn: Compare vectors
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2018-01-23 17:46:28 +00:00 |
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MerryMage
|
2b59e2ba0b
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microinstruction: bug: Add missing opcodes
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2018-01-23 17:46:28 +00:00 |
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Lioncash
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bd00d9bc80
|
A64: Implement SMADDL, SMSUBL, UMADDL, and UMSUBL
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2018-01-23 16:08:05 +00:00 |
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Lioncash
|
768e5bcf9c
|
A64: Implement MADD and MSUB
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2018-01-23 16:08:05 +00:00 |
|
Lioncash
|
ffaf837e58
|
A64: Implement CLZ
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2018-01-23 11:55:09 +00:00 |
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Lioncash
|
585e77d20e
|
opcodes: Add 64-bit CountLeadingZeroes opcode
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2018-01-23 11:55:09 +00:00 |
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MerryMage
|
f2dc9c7727
|
data_processing_register: Clean-up
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2018-01-22 22:47:01 +00:00 |
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Lioncash
|
efa67caf5f
|
A64: Implement HINT, NOP, YIELD, WFE, WFI, SEV, and SEVL
Truly the most difficult A64 instructions to implement.
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2018-01-22 11:54:12 +00:00 |
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Lioncash
|
692cd6f27b
|
A64: Implement ASRV, LSLV, LSRV, and RORV
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2018-01-22 11:51:46 +00:00 |
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Lioncash
|
a5978a01ca
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data_processsing_conditional_select: Implement CSINC, CSINV and CSNEG
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2018-01-21 23:33:18 +00:00 |
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Lioncash
|
48e4e021f7
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a32/a64_emit_x64: Remove unused includes
|
2018-01-21 20:09:23 +00:00 |
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