Tillmann Karras
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0718ee4482
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decoder_detail: use structured bindings
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2018-05-12 11:15:39 +01:00 |
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Lioncash
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e0faf3277e
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simd_two_register_misc: Handle 64-bit case for SCVTF_int_4
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2018-05-08 18:14:50 +01:00 |
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Lioncash
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b166981ff5
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ir: Add opcode to perform the vector conversion S64->F64
Unfortunately x86 prior to AVX-512 doesn't really give us any convenient instruction to do the work for us
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2018-05-08 18:14:50 +01:00 |
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Lioncash
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4d2c5184ff
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A64: Implement SHLL/SHLL2
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2018-05-08 17:57:55 +01:00 |
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Lioncash
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ae57f6eb58
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A64: Add missing decoding for PRFM (unscaled offset)
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2018-05-08 15:01:53 +01:00 |
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Lioncash
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3e0861d013
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A64: Implement UHSUB
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2018-05-07 19:04:10 +01:00 |
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Lioncash
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93255e6dbd
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A64: Implement SHSUB
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2018-05-07 19:04:10 +01:00 |
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Lioncash
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a0e3943ade
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ir: Add opcodes for performing vector halving subtracts
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2018-05-07 19:04:10 +01:00 |
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Lioncash
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b4a2d497f9
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A64: Implement SM4EKEY
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2018-05-07 19:01:22 +01:00 |
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Lioncash
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4372700ec9
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A64: Implement SM4E
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2018-05-07 19:01:22 +01:00 |
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Lioncash
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284afd18cb
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ir: Add an opcode for doing an SM4 lookup table query
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2018-05-07 19:01:22 +01:00 |
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Lioncash
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6d0b58039e
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A64: Implement UHADD
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2018-05-07 16:39:17 +01:00 |
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Lioncash
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e4efd365fb
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A64: Implement SHADD
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2018-05-07 16:39:17 +01:00 |
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Lioncash
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1da4671b53
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ir: Add opcodes for performing halving adds
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2018-05-07 16:39:17 +01:00 |
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Lioncash
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7a066fb011
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disassembler_arm: Remove rotation helper function in favor of Common::RotateRight
Mildly reduces the amount of duplicated behavior
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2018-05-02 17:14:13 +01:00 |
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Lioncash
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8aa9a47a6a
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A64: Implement SSHL (scalar)
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2018-04-30 22:41:17 +01:00 |
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Lioncash
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8818d76212
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A64: Implement SSHL (vector)
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2018-04-30 22:41:17 +01:00 |
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Lioncash
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3e3ce37eb8
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backend_x64/ir: Amend generic LogicalVShift() template to also handle signed variants
Also adds IR opcodes to dispatch said variants
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2018-04-30 22:41:17 +01:00 |
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Lioncash
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fea1e6ca1f
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A64: Implement CMTST's scalar variant
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2018-04-28 19:17:38 +01:00 |
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Lioncash
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2a35b2a46a
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A64: Implement UZP1 and UZP2
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2018-04-26 08:49:51 +01:00 |
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Lioncash
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9c2550ac72
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ir: Add opcodes for performing vector deinterleaving
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2018-04-26 08:49:51 +01:00 |
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Lioncash
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4765503fc6
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A64: Implement FNEG (half-precision)
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2018-04-26 08:49:03 +01:00 |
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Lioncash
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96be76296e
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A64: Implement USHL (scalar)
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2018-04-24 08:15:00 +01:00 |
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Lioncash
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8261911bd8
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A64: Implement FNEG (vector)
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2018-04-24 08:14:31 +01:00 |
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Lioncash
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633e8e3ecd
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A64: Implement RSUBHN/RSUBHN2
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2018-04-23 21:08:43 +01:00 |
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Lioncash
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4dec013b09
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A64: Implement RADDHN/RADDHN2
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2018-04-23 21:08:43 +01:00 |
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Lioncash
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7fb04ccb36
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A64: Implement XAR
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2018-04-23 16:05:40 +01:00 |
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Lioncash
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db29d68a2d
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simd_two_register_misc: Factor out common comparison code
Gets rid of a tiny bit of duplicated code.
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2018-04-23 16:04:58 +01:00 |
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Lioncash
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1692e26c2e
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A64: Implement CMLE (zero)'s vector variant
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2018-04-23 16:04:58 +01:00 |
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Lioncash
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21936a82aa
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A64: Implement CMTST (vector)
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2018-04-23 16:04:40 +01:00 |
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Lioncash
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4f27764191
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A64: Implement ADDHN{2} and SUBHN{2}
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2018-04-21 08:58:16 +01:00 |
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Lioncash
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1791114ab1
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translate: zero extend result in Vpart when storing to lower part of vector
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2018-04-21 08:58:16 +01:00 |
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Lioncash
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f6e624e9ea
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A64: Implement CMLE (zero)'s scalar variant
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2018-04-20 17:31:07 +01:00 |
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Lioncash
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41a3e87c15
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A64: Implement CMLT (zero)'s scalar single/double-precision variant
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2018-04-20 15:48:50 +01:00 |
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Lioncash
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51912ca6ab
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A64: Implement SHA512H2
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2018-04-20 07:29:26 +01:00 |
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Lioncash
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4655f78ec2
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A64: Implement SHA512H
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2018-04-20 07:29:26 +01:00 |
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Lioncash
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3a52275611
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A64: Handle S32->F32 case for SCVTF (vector)
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2018-04-19 21:09:42 +01:00 |
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Lioncash
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230e954e5c
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IR: Add opcode for packed word->f32 conversions
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2018-04-19 21:09:42 +01:00 |
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Lioncash
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f24cfba5c2
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A64: Implement SHA512SU1
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2018-04-19 19:51:31 +01:00 |
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Lioncash
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e3412d9779
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A64: Implement SHA512SU0
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2018-04-19 19:51:31 +01:00 |
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Lioncash
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cc76802990
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A64: Implement SHA256H and SHA256H2
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2018-04-19 19:50:17 +01:00 |
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MerryMage
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b5585baefb
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A64: Implement SCVTF (vector, integer), scalar varaint
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2018-04-19 19:48:45 +01:00 |
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MerryMage
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badc7ac467
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impl: Reorganize scalar two-register misc instructions
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2018-04-19 19:48:45 +01:00 |
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Lioncash
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d53decf9e1
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A64: Implement SHA256SU1
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2018-04-19 08:40:55 +01:00 |
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Lioncash
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62be988507
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simd_two_register_misc: Add missing zeroing of the vector for CMGT and CMLT
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2018-04-19 08:39:56 +01:00 |
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Lioncash
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cd5fee6746
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A64: Implement CMGE (zero)'s vector variant
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2018-04-19 08:39:56 +01:00 |
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Lioncash
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da99e1fdaa
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A64: Implement MLS (by element)
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2018-04-19 08:39:25 +01:00 |
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Lioncash
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8920238d59
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A64: Implement MUL (by element)
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2018-04-19 08:39:25 +01:00 |
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MerryMage
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68d6a1276b
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A64: Implement MLA (by element)
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2018-04-19 00:04:52 +01:00 |
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Lioncash
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7340c36ae0
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A64: Implement ABS (scalar)
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2018-04-19 00:03:08 +01:00 |
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