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Author SHA1 Message Date
Lioncash
0d1f9841d1
constant_propagation_pass: Fold OR operations 2018-10-01 18:53:54 -04:00
Lioncash
142978041d
constant_propagation_pass: Fold AND operations 2018-10-01 18:53:54 -04:00
Lioncash
be3ba545e7
ir/value: Add member function to check whether or not all bits of a contained value are set 
This is useful when we wish to know if a contained value is something
like 0xFFFFFFFF, as this helps perform constant folding. For example the
operation: x & 0xFFFFFFFF can be folded to just x in the 32-bit case.
 2018-10-01 18:53:47 -04:00
Lioncash
f5233bfc69
constant_propagation_pass: Fold EOR operations 
It's possible to fold cases of exclusive OR operations if they can be
known to be an identity operation, or if both operands happen to be known
immediates, in which case we can just store the result of the
exclusive-OR directly.
 2018-09-29 03:59:15 -04:00
Lioncash
41ba9fd7bc value: Move ImmediateToU64() to be a part of Value's interface 
This'll make it slightly nicer to do basic constant folding for 32-bit
and 64-bit variants of the same IR opcode type. By that, I mean it's
possible to inspect immediate values without a bunch of conditional
checks beforehand to verify that it's possible to call GetU32() or
GetU64, etc.
 2018-09-28 22:19:11 +01:00
MerryMage
c6a6271f86 reg_alloc: Emit AVX instructions where able 
Smaller codesize.
 2018-09-28 21:12:48 +01:00
MerryMage
aedd32aa20 abi: Emit AVX instructions where able 
Smaller codesize.
 2018-09-28 21:12:17 +01:00
MerryMage
f2d9337663 a64_exclusive_monitor: Loosen memory ordering requirements 
It is not necessary to be as strict as it was.
 2018-09-27 16:21:56 +01:00
Lioncash
7ca709de81 travis: Make macOS builds use Xcode 10 
Keeps the toolchain up to date and allows the use of things like
<optional> and <variant> from the standard library.
 2018-09-25 19:23:51 +01:00
MerryMage
14dd45eed9 Fix VShift terminology 
An arithmetic shift is by definition a signed shift, and a logical shift is by definition an unsigned shift.

- Rename VectorLogicalVShiftS* -> VectorArithmeticVShift*
- Rename VectorLogicalVShiftU* -> VectorLogicalVShift*
 2018-09-23 10:50:39 +01:00
MerryMage
88554c4f04 emit_x64_vector: AVX512 implementation of EmitVectorLogicalVShiftS16 2018-09-23 10:41:41 +01:00
MerryMage
ab4e316b24 emit_x64_vector: AVX512 implementation of EmitVectorLogicalVShiftS64 2018-09-23 10:41:30 +01:00
MerryMage
0ea84f34fe emit_x64_vector: AVX2 implementation of EmitVectorLogicalVShiftS32 2018-09-23 10:41:10 +01:00
MerryMage
c77a2c5bab emit_x64_vector: AVX512 implementation of EmitVectorLogicalVShiftU16() 2018-09-23 10:14:20 +01:00
MerryMage
e9441fd561 emit_x64_vector: AVX2 implementation of EmitVectorLogicalVShiftU64() 2018-09-23 10:14:20 +01:00
MerryMage
0e9c33cbf3 emit_x64_vector: AVX2 implementation of EmitVectorLogicalVShiftU32() 2018-09-23 10:14:20 +01:00
Lioncash
8f8527407c emit_x64_vector: SSSE3 variant of EmitVectorCountLeadingZeros8() 
pshufb lyfe
 2018-09-23 10:13:08 +01:00
Mat M
be05e75818
Merge pull request #397 from VelocityRa/dec-shift-fix 
decoders: Cast to correctly-sized type before shifting
 2018-09-22 19:17:36 -04:00
VelocityRa
bc328fc645 decoders: Cast to correctly-sized type before shifting 
Fixes decoding for 64-bit instructions

Does not help/apply to any currently supported ARM versions (since
all are 32-bit length or below), it's for future-proofing should
such an arch be supported.
 2018-09-22 22:10:29 +03:00
MerryMage
9c3d2d104d a64_emit_x64: Lowercase PAGE_SIZE 
PAGE_SIZE is defined as a macro by musl.
 2018-09-22 18:54:49 +01:00
MerryMage
f538d29be7 emit_x64_vector_floating_point: SSE4.1 implementation of EmitFPVectorToFixed 2018-09-22 18:47:15 +01:00
MerryMage
1603a6e9f8 emit_x64_vector_floating_point: EmitFPVectorRoundInt: Use FCODE 2018-09-22 16:19:54 +01:00
MerryMage
2e1ccaff53 emit_x64_vector: AVX implementation for EmitVectorCountLeadingZeros8 2018-09-22 16:08:23 +01:00
MerryMage
555bfdacf9 emit_x64_vector: SSE implementation of EmitVectorCountLeadingZeros16 2018-09-22 13:05:47 +01:00
Lioncash
71c2589662
externals: Update Xbyak to 5.73 
Merge commit '1ec1b2febb1eac58cf98384dd8ba977a74be7054' into xbyak
 2018-09-19 17:55:45 -04:00
Lioncash
1ec1b2febb Squashed 'externals/xbyak/' changes from 1de435ed..42462ef9 
42462ef9 use evex encoding for vpslld/vpslldq/vpsraw/...(reg, mem, imm);
da9117a9 update version of readme.md
d35f4fb7 fix the encoding of vinsertps for disp8N

git-subtree-dir: externals/xbyak
git-subtree-split: 42462ef922893f0d3f2156d005fa27ba6898498b
 2018-09-19 17:54:43 -04:00
MerryMage
171d11659d A64: Implement SCVTF, UCVTF (vector, fixed-point), scalar variant 2018-09-19 20:11:14 +01:00
MerryMage
f221bb0095 emit_x64_floating_point: Reduce fallback LUT code in EmitFPToFixed 2018-09-19 20:11:14 +01:00
MerryMage
eb123e2a74 A64: Implement FCVTZS, FCVTZU, UCVTF, SCVTF (vector, fixed-point), vector variant 2018-09-19 19:47:28 +01:00
Lioncash
487d37a4a1 A64: Implement UQSHL's vector immediate and register variants 2018-09-19 12:13:22 +01:00
Lioncash
f69893345f ir: Add opcodes for unsigned saturating left shifts 2018-09-19 12:13:22 +01:00
Lioncash
7148e661f6 A64/translate/impl: Make signatures consistent for unimplemented by-element SIMD variants 
Makes them all consistent, so it isn't necessary to change the
prototypes over when implementing them.
 2018-09-19 12:11:35 +01:00
Lioncash
fdde4ca363 A64: Implement BRK 
Currently, we can just implement this as part of the exception
interface, similar to how it's done for the A32 interface with BKPT.
 2018-09-19 07:09:27 +01:00
Lioncash
b1490db0e9 A64/imm: Add full range of comparison operators to Imm template 
Makes the comparison interface consistent by providing all of the
relevant members. This also modifies the comparison operators to take
the Imm instance by value, as it's really only a u32 under the covers,
and it's cheaper to shuffle around a u32 than a 64-bit pointer address.
 2018-09-19 07:09:00 +01:00
MerryMage
1ec40ef6ed IR: Add fbits argument to FPVectorFrom{Signed,Unsigned}Fixed 2018-09-18 21:46:17 +01:00
MerryMage
d6d5e986c2 A64: Implement SCVTF, UCVTF (scalar, fixed-point) 2018-09-18 21:08:06 +01:00
MerryMage
6513595c09 opcodes.inc: Align columns to a tabstop of 4 2018-09-18 20:37:03 +01:00
MerryMage
6b0d2b529e IR: Add fbits argument to FixedToFP-related opcodes 2018-09-18 20:36:37 +01:00
Lioncash
c4b383124f A64: Implement SQSHL's vector immediate variant 2018-09-18 18:22:03 +01:00
Lioncash
e0d8d2d855 A64: Implement SQSHL's vector register variant 2018-09-18 18:22:03 +01:00
Lioncash
532762582b ir: Add opcodes for left signed saturated shifts 2018-09-18 18:22:03 +01:00
Lioncash
9705252968 branch: Make variables const where applicable 2018-09-18 17:45:49 +01:00
Lioncash
650946e41c move_wide: Make variables const where applicable 2018-09-18 17:45:49 +01:00
Lioncash
62b3a6dcfb load_store_register_unprivileged: Make variables const where applicable 2018-09-18 17:45:49 +01:00
Lioncash
3add1c7b3f load_store_register_immediate: Place conditional bodies on their own line 
Makes the conditionals visually consistent with the rest of the
codebase.
 2018-09-18 17:45:49 +01:00
Lioncash
2fc4088a74 load_store_load_literal: Make variables const where applicable 2018-09-18 17:45:49 +01:00
Lioncash
b2c146259f data_processing_logical: Move datasize declarations after early-exit conditionals 
While we're at it, make variables const where applicable.
 2018-09-18 17:45:49 +01:00
Lioncash
028028f9eb data_processing_conditional_select: Make variables const where applicable 
Makes CSEL's function consistent with all of the others.
 2018-09-18 17:45:49 +01:00
Lioncash
c66042da57 data_processing_addsub: Move datasize declarations after early-exit conditionals 
While we're at it, also make relevant variables const where applicable
 2018-09-18 17:45:49 +01:00
Lioncash
6bc546e1f7 data_processing_bitfield: Move datasize variables after early-exit conditionals 
Moves the declaration of datasize to the scope that it's used within.
This also takes the opportunity to apply const where applicable, and
make early-exits all vertically consistent with one another.
 2018-09-17 18:14:16 +01:00