MerryMage
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229ff47738
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Merge branch 'feature/exclusive-mem'
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2018-02-13 12:53:29 +00:00 |
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MerryMage
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43f27b3e15
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A64: Implement STXP, STLXP, LDXP, LDAXP
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2018-02-13 12:50:50 +00:00 |
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MerryMage
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11eb8c2bea
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A64: Implement CLREX
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2018-02-13 12:31:16 +00:00 |
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MerryMage
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22285842af
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A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
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2018-02-13 12:30:58 +00:00 |
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MerryMage
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d7323d6799
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fuzz_with_unicorn: Speed up tests by not initializing/tearing down constantly
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2018-02-12 21:48:29 +00:00 |
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MerryMage
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eac0933738
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Merge branch 'feature/direct-page-table-access'
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2018-02-12 21:47:43 +00:00 |
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MerryMage
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49f1de3188
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Direct Page Table Access: Handle address spaces less than the full 64-bit in size
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2018-02-12 21:26:23 +00:00 |
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MerryMage
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406725e533
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Implement direct page table access
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2018-02-12 20:51:03 +00:00 |
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MerryMage
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adc2d5a3cc
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fuzz_with_unicorn: Fix read-past-end access via jit_iter
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2018-02-12 20:51:03 +00:00 |
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MerryMage
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885e092f99
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callbacks: Member functions should be const
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2018-02-12 20:51:03 +00:00 |
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MerryMage
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9598bd45ef
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a64_emit_x64: Implement {Read,Write}Memory128 in terms of a function call
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2018-02-12 18:26:08 +00:00 |
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MerryMage
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276326e0e8
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abi: Add RAX to ABI_ALL_CALLER_SAVE
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2018-02-12 18:17:39 +00:00 |
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MerryMage
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7a161ed35c
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A64: Partially implement MRS
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2018-02-12 00:06:44 +00:00 |
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MerryMage
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b733479b5e
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A64: Implement DSB, DMB
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2018-02-11 23:27:28 +00:00 |
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MerryMage
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1ba2642742
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Implement DC instructions
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2018-02-11 23:12:28 +00:00 |
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Lioncash
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e12fa19142
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A64: Implement NOT (vector)
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2018-02-11 20:14:03 +00:00 |
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MerryMage
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1b836b6deb
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IR: Implement FPMax, FPMin
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2018-02-11 16:43:47 +00:00 |
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MerryMage
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94115d1775
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A64: Implement FADD (vector), vector variant
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2018-02-11 16:30:03 +00:00 |
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MerryMage
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24def19cd7
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IR: Implement FPVectorAdd
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2018-02-11 16:29:48 +00:00 |
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MerryMage
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9379d54a44
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A64: Implement SSHLL, SSHLL2
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2018-02-11 16:24:55 +00:00 |
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MerryMage
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a7e4202828
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IR: Implement VectorSignExtend
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2018-02-11 16:24:33 +00:00 |
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MerryMage
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01760f1a21
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CMakeLists: Ignore warnings within xbyak
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2018-02-11 14:57:35 +00:00 |
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MerryMage
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ae7d118f22
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A64: Implement DUP (element), vector variant
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2018-02-11 14:34:13 +00:00 |
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MerryMage
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b87814ce88
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load_store_multiple_structures: Improve IR codegen for selem == 1 case
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2018-02-11 12:48:49 +00:00 |
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MerryMage
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6113346a5b
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A64: Implement FSUB (vector)
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2018-02-11 12:18:05 +00:00 |
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MerryMage
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8c6fce20d2
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IR: Implement FPVectorSub
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2018-02-11 12:17:53 +00:00 |
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MerryMage
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3fffeadf0d
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emit_x64_vector: EmitOneArgumentFallback
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2018-02-11 11:59:43 +00:00 |
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MerryMage
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4df6c424df
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Forward declare IR::Opcode and IR::Type where possible
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2018-02-11 11:52:44 +00:00 |
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MerryMage
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09632954d7
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A64: Implement CNT
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2018-02-11 11:52:44 +00:00 |
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MerryMage
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c2c9ea85a5
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IR: Implement VectorPopulationCount
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2018-02-11 11:52:44 +00:00 |
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MerryMage
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0996d4fd2e
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A64: Implement MLS (vector)
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2018-02-11 11:04:46 +00:00 |
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MerryMage
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5319f6af95
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A64: Implement MLA (vector)
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2018-02-11 11:00:16 +00:00 |
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MerryMage
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17519df3e8
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emit_x64_vector: Add SSE4.1 implementation for EmitVectorMultiply64
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2018-02-11 10:47:22 +00:00 |
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MerryMage
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eac6a56a4b
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emit_x64_vector: More explicit lambda decay
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2018-02-11 10:47:00 +00:00 |
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MerryMage
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727b1b0b51
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A64: Implement MUL (vector)
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2018-02-11 10:18:47 +00:00 |
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MerryMage
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80fce9c4b9
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IR: Implement VectorMultiply
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2018-02-11 10:18:29 +00:00 |
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MerryMage
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cb65a26da2
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emit_x64_vector: Order alphabetically
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2018-02-11 09:41:37 +00:00 |
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MerryMage
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2b968981a1
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A64: Implement STR (register, SIMD&FP), LDR (register, SIMD&FP)
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2018-02-11 01:06:26 +00:00 |
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MerryMage
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7681159811
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decoder/a64: Don't rearrange unrelated decoders
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2018-02-11 00:43:33 +00:00 |
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MerryMage
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56fe848e4e
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A64: Implement SUB (vector)
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2018-02-10 23:58:33 +00:00 |
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MerryMage
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b429efa081
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A64: Implement SIMD instruction SSRA, vector variant
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2018-02-10 23:30:00 +00:00 |
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MerryMage
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0a96a437cb
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A64: Implement SIMD instruction SSHR, vector variant
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2018-02-10 23:28:05 +00:00 |
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MerryMage
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a5299d0be5
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IR: Implement VectorArithmeticShiftRight
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2018-02-10 23:27:46 +00:00 |
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MerryMage
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8e8068cfaf
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impl: Improve Vpart setter
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2018-02-10 17:05:52 +00:00 |
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MerryMage
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5ffa84f41d
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A64: Implement SIMD instructions XTN, XTN2
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2018-02-10 17:01:33 +00:00 |
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MerryMage
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dc9785bdcd
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IR: Implement VectorNarrow
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2018-02-10 17:01:33 +00:00 |
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MerryMage
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ebc594385c
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constant_pool: Allow for 128-bit constants
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2018-02-10 16:36:00 +00:00 |
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MerryMage
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8e23683b63
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emit_x64_vector: Add SSE4.1 implementations for VectorZeroExtend
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2018-02-10 16:24:43 +00:00 |
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MerryMage
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d9f803924e
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IR: Implement VectorSub
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2018-02-10 11:25:50 +00:00 |
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MerryMage
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c01bbbd09d
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A64: Implement SIMD instruction USRA, vector variant
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2018-02-10 11:12:54 +00:00 |
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