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1655 Commits

Author SHA1 Message Date
Lioncash
28eedda6ff
frontend/A64/types: Make RegNumber() and VecNumber() constexpr 
Given they simply perform casting, they can be safely made constexpr.
 2019-05-02 00:00:15 -04:00
Lioncash
455a7a0359
frontend/A64/types: Use helper functions in operator+ overloads 
Allows us to get rid of another explicit cast.
 2019-05-01 23:59:20 -04:00
Lioncash
08cd3f0385
frontend/ir/ir_emitter: Apply const to locals where applicable 
Makes const usage consistent with all other functions in the source
file.
 2019-05-01 23:54:22 -04:00
Lioncash
967d1fcc8d
frontend/ir/ir_emitter: Use switch constructs in floating point opcodes where applicable 
This'll reduce the amount of noise necessary in changes implementing
half-precision instructions, as the type can just be prepended to the
switch cases, instead of rewriting the whole if/else branch.
 2019-05-01 23:45:01 -04:00
Lioncash
2bd54d6485
A32: Resolve parameter discrepancies discovered via use of the Imm template 2019-04-30 23:58:39 -04:00
Lioncash
17815bdda3
A32: Replace immediate type aliases with the Imm template 
Replaces type aliases of raw integral types with the more type-safe Imm
template, like how the AArch64 frontend has been using it.

This makes the two frontends more consistent with one another.
 2019-04-28 07:31:00 -04:00
Lioncash
f17bf4a352
A32/barrier: Correct PC assignment within ISB 
The SetRegister() IR function doesn't allow specifying the PC as a
register. This is a discrepancy that slipped through (my bad). Instead,
we can use BranchWritePC(), like how the other similar PC modifying
locations do it.
 2019-04-27 17:22:32 -04:00
Lioncash
4ed37614c6
frontend: Move imm.h to the top-level directory of the frontends 
Preparation to utilize the immediate type within the A32 backend as
well, which will allow eliminating numerous type aliases like Imm4,
Imm5, etc.
 2019-04-27 14:53:33 -04:00
Lioncash
6201b0e32d
A32/disassembler_arm: Mark utility functions as static where applicable 
These don't depend on class state and can be marked static to make that
explicit.
 2019-04-27 09:45:15 -04:00
Lioncash
f3679e6278
A32: Implement barrier instructions introduced in ARMv7 
Provides basic implementations of the barrier instruction introduced
within ARMv7. Currently these simply mirror the behavior of the AArch64
equivalents.
 2019-04-27 08:29:49 -04:00
Lioncash
23571f99c5
A32: Implement ARM-mode MLS 2019-04-26 06:50:03 -04:00
Lioncash
adf04f6f9a
A32: Implement ARM-mode MOVT 2019-04-26 06:50:03 -04:00
Lioncash
b4429e7f55
A32: Implement ARM-mode SBFX 2019-04-26 06:50:03 -04:00
Lioncash
42964964ce
A32: Implement ARM-mode UBFX 2019-04-26 06:50:03 -04:00
Lioncash
745dfd5046
A32: Implement ARM-mode BFI 2019-04-26 06:50:02 -04:00
Lioncash
20e499d8d6
A32: Implement ARM-mode BFC 2019-04-26 06:50:02 -04:00
Lioncash
3b7b50b0c0
A32: Implement ARM-mode RBIT 2019-04-26 06:49:56 -04:00
Lioncash
c62b822937
A32: Implement ARM-mode SDIV/UDIV 
Now that we have Unicorn in place, we can freely implement instructions
introduced in newer versions of the ARM architecture.
 2019-04-21 21:30:29 -04:00
Lioncash
127efc592d
A32/translate_thumb: Clean up formatting 
Performs a similar tidying up of the Thumb translator, like what was
done with the regular ARM translator to make it consistent with the rest
of the codebase.

The A32 backend (both Thumb and ARM), will likely see more changes to it
in the near future, so this just acts as a "dusting off".
 2019-04-20 00:32:25 -04:00
Merry
7316ab18f6
Merge pull request #483 from lioncash/invert 
frontend/ir/cond: Remove unused invert() function
 2019-04-17 10:45:34 +01:00
Lioncash
66e3b1c1eb
common/fp/op/FPConvert: Remove unnecessary casts in FPConvert() 
These were made unnecessary in 2c2fdb435cf8e358a0c5b907ce8131e434df3f22,
but were missed during the initial removal.
 2019-04-16 21:53:22 -04:00
Lioncash
fe7c21b687
frontend/ir/cond: Remove unused invert() function 
This is no longer used by anything in the codebase, so it can be
removed.
 2019-04-16 21:37:12 -04:00
Merry
6377fd9866
Merge pull request #482 from lioncash/fixedfp 
A64: Handle half-precision variants of FP->Fixed instructions
 2019-04-15 20:08:01 +01:00
MerryMage
732215d68d emit_x64_data_processing: Remove INVALID_REG 
INVALID_REG.cvt8() now throws
 2019-04-15 16:59:39 +01:00
Lioncash
105d4ed9e5
A64: Handle half-precision variants of FP->Fixed-point instructions 2019-04-15 08:50:00 -04:00
Merry
d32f648578
Merge pull request #481 from lioncash/alloc 
ir/basic_block: Forward declare headers where applicable
 2019-04-15 13:04:02 +01:00
Lioncash
f4d0a09bf4
ir/basic_block: Forward declare headers where applicable 
Now that the constructor and destructors have been placed within the cpp
file, we can forward declare the memory pool data structures. Now, a
change to the memory pool code won't ripple across the entirety of the
IR emitter.
 2019-04-15 06:00:35 -04:00
Lioncash
db78e2f32c
ir/block: Default ctor and dtor in the cpp file 
Prevents potentially inlining allocation code everywhere. While we're at
it, also explicitly delete/default the copy/move constructor/assignment
operators to be explicit about them.
 2019-04-15 05:58:36 -04:00
Lioncash
2c2fdb435c
common/fp/info: Make half-precision info struct functions return correctly sized types 
While initially done to potentially prevent creating bugs due to C++
having a silly type-promotion mechanism involving types < sizeof(int)
and unsignedness, given that the bulk of these functions' usages
are on exit paths, these can return the correct type to avoid the need
to cast at every usage point.
 2019-04-15 04:55:00 -04:00
Lioncash
189692246d
frontend/ir/microinstruction: Add missing fixed-point opcodes to ReadsFromAndWritesToFPSRCumulativeExceptionBits() 2019-04-15 00:55:49 -04:00
Lioncash
1d3fc42bfe
frontend/ir_emitter: Add half-precision->fixed-point opcodes 2019-04-15 00:55:46 -04:00
Lioncash
6c7de6c9c4
common/fp/op/FPToFixed: Add half-precision specialization of FPToFixed 2019-04-15 00:17:44 -04:00
Lioncash
28e0f4fe59
A64: Implement FRSQRTS' half-precision vector variant 2019-04-14 21:12:54 -04:00
Lioncash
6f7a370cfb
A64: Implement FRSQRTS' half-precision scalar variant 
With the necessary machinery in place, we can now handle the
half-precision variant.
 2019-04-14 21:12:54 -04:00
Lioncash
793b3b38d4
frontend/ir_emitter: Add half-precision opcode variant of FPVectorRSqrtStepFused 2019-04-14 21:12:54 -04:00
Lioncash
db4d134726
frontend/ir_emitter: Add half-precision opcode variant of FPRSqrtStepFused 2019-04-14 21:12:49 -04:00
Lioncash
cff4394717
common/fp/op/FPRSqrtStepFused: Add half-precision specialization for FPRSqrtStepFused 2019-04-14 20:51:58 -04:00
Merry
eea732febf
Merge pull request #478 from lioncash/stepfused 
A64: Handle half-precision variants of FRECPE and FRECPS
 2019-04-14 12:40:18 +01:00
Lioncash
b67cc72213
A64: Implement half-precision vector variant of FRECPE 2019-04-14 06:14:20 -04:00
Lioncash
4b3f5b8a30
A64: Implement half-precision scalar variant of FRECPE 2019-04-14 06:14:20 -04:00
Lioncash
4519e4641c
A64: Implement half-precision vector variant of FRECPS 2019-04-14 06:14:19 -04:00
Lioncash
abcf1a6e09
A64: Implement half-precision scalar variant of FRECPS 2019-04-14 06:14:19 -04:00
Lioncash
c55db96819
frontend/ir_emitter: Add half-precision opcode for FPVectorRecipEstimate 2019-04-14 06:14:19 -04:00
Lioncash
1615ba0adc
frontend/ir_emitter: Add half-precision opcode for FPRecipEstimate 2019-04-14 06:14:19 -04:00
Lioncash
e93161e25b
common/fp/op: Add half-precision specialization for FPRecipEstimate 2019-04-14 06:14:19 -04:00
Lioncash
4ae0a27ea4
frontend/ir_emitter: Add half-precision opcode for FPVectorRecipStepFused 2019-04-14 06:14:19 -04:00
Lioncash
065143b395
frontend/ir_emitter: Add half-precision opcode for FPRecipStepFused 2019-04-14 06:14:18 -04:00
Lioncash
408bbfb766
common/fp/op: Add half-precision specialization for FPRecipStepFused 2019-04-14 06:13:43 -04:00
Lioncash
e35352b69e
A64: Implement half-precision variant of FRSQRTE's vector variant 2019-04-14 06:12:20 -04:00
Lioncash
0f677744bb
A64: Implement half-precision variant of FRSQRTE's scalar variant 2019-04-14 06:12:20 -04:00