1973 Commits

Author SHA1 Message Date
Mat M
d88e1d027d
Merge pull request #487 from lioncash/fuzz2
a32/fuzz_arm: Use same fuzzing mechanism as AArch64
2019-04-27 09:42:46 -04:00
Merry
19c59bbf26
Merge pull request #486 from lioncash/barrier
A32: Implement barrier instructions introduced in ARMv7
2019-04-27 14:40:06 +01:00
Lioncash
f3679e6278
A32: Implement barrier instructions introduced in ARMv7
Provides basic implementations of the barrier instruction introduced
within ARMv7. Currently these simply mirror the behavior of the AArch64
equivalents.
2019-04-27 08:29:49 -04:00
Lioncash
c32a10ca7e
a32/fuzz_arm: Use same fuzzing mechanism as AArch64
Introduces the same fuzzing mechanism used by the AArch64 code for
fuzzing instruction implementations, getting rid of the need to
manually specify the instruction generator sequences--replacing it with
an instruction blacklist instead.

Much of this change originates from a previous patch made by Mary. This
just makes it interact nicely with the alterations made to get Unicorn
to cooperate properly.
2019-04-27 06:11:55 -04:00
Mat M
b27fe43120
Merge pull request #485 from lioncash/a32
A32: Handle all ARM-mode arithmetic and data processing instructions added in ARMv6T2 and ARMv7
2019-04-26 06:51:24 -04:00
Lioncash
23571f99c5
A32: Implement ARM-mode MLS 2019-04-26 06:50:03 -04:00
Lioncash
adf04f6f9a
A32: Implement ARM-mode MOVT 2019-04-26 06:50:03 -04:00
Lioncash
b4429e7f55
A32: Implement ARM-mode SBFX 2019-04-26 06:50:03 -04:00
Lioncash
42964964ce
A32: Implement ARM-mode UBFX 2019-04-26 06:50:03 -04:00
Lioncash
745dfd5046
A32: Implement ARM-mode BFI 2019-04-26 06:50:02 -04:00
Lioncash
20e499d8d6
A32: Implement ARM-mode BFC 2019-04-26 06:50:02 -04:00
Lioncash
3b7b50b0c0
A32: Implement ARM-mode RBIT 2019-04-26 06:49:56 -04:00
Lioncash
c62b822937
A32: Implement ARM-mode SDIV/UDIV
Now that we have Unicorn in place, we can freely implement instructions
introduced in newer versions of the ARM architecture.
2019-04-21 21:30:29 -04:00
Lioncash
9110e70bd3
travis: Re-enable A32 tests 2019-04-20 06:02:32 -04:00
Lioncash
79af6c118c
a32_unicorn: Silence PC value assertions
Ensure the PC is properly masked off after a run.
2019-04-20 06:02:29 -04:00
Lioncash
43422bc106
travis: Amend build parameters
Currently just run the 64-bit tests.
2019-04-20 05:22:54 -04:00
Lioncash
0d3764569d
fuzz_arm: Tidy up existing tests
Now that we utilize C++17, we can use std::array's deduction guides to
avoid the need to explicitly specify the template arguments.

While we're at it, also use const where applicable.
2019-04-20 05:00:15 -04:00
Lioncash
27e8a41b7f
Merge branch 'fuzz' 2019-04-20 04:19:37 -04:00
Lioncash
bce91ff07b
dynarmic_tests: Remove skyeye interpreter
This is quite a messy interpreter and would require a large amount of
work to bring it up to speed to begin implementing newer portions of the
AArch32 instruction set into Dynarmic.

Given we already have fuzzing with Unicorn set up for
AArch64/AArch32, we can get rid of this and unify our testing
infrastructure.

This will also make building the tests much faster, given a whole
interpreter doesn't need to be built anymore as part of the project.
2019-04-20 04:19:22 -04:00
Lioncash
ad7d439ef5
A32: Fuzz instructions using unicorn
While skyeye was OK previously, now that we have an AArch64 backend,
this also means that we eventually have to support the AArch32
counterpart to it. Unfortunately, SkyEye is only compatible up to
ARMv6K, so we woud need to do a lot of work to bring the interpreter up
to speed with things to even begin testing new instruction
implementations.

For the AArch64 side of things, we already use Unicorn, so we can toss
out SkyEye in favor of it instead.
2019-04-20 04:17:18 -04:00
Lioncash
127efc592d
A32/translate_thumb: Clean up formatting
Performs a similar tidying up of the Thumb translator, like what was
done with the regular ARM translator to make it consistent with the rest
of the codebase.

The A32 backend (both Thumb and ARM), will likely see more changes to it
in the near future, so this just acts as a "dusting off".
2019-04-20 00:32:25 -04:00
Merry
7316ab18f6
Merge pull request #483 from lioncash/invert
frontend/ir/cond: Remove unused invert() function
2019-04-17 10:45:34 +01:00
Lioncash
66e3b1c1eb
common/fp/op/FPConvert: Remove unnecessary casts in FPConvert()
These were made unnecessary in 2c2fdb435cf8e358a0c5b907ce8131e434df3f22,
but were missed during the initial removal.
2019-04-16 21:53:22 -04:00
Lioncash
fe7c21b687
frontend/ir/cond: Remove unused invert() function
This is no longer used by anything in the codebase, so it can be
removed.
2019-04-16 21:37:12 -04:00
Merry
6377fd9866
Merge pull request #482 from lioncash/fixedfp
A64: Handle half-precision variants of FP->Fixed instructions
2019-04-15 20:08:01 +01:00
MerryMage
732215d68d emit_x64_data_processing: Remove INVALID_REG
INVALID_REG.cvt8() now throws
2019-04-15 16:59:39 +01:00
MerryMage
731aa2df8d externals: Update xbyak to 73ac586
Merge commit 'b0bc810667409c2fddd4e8c7a28ea4b1ffa76a03'
2019-04-15 16:18:43 +01:00
MerryMage
b0bc810667 Squashed 'externals/xbyak/' changes from 4a6fac8a..73ac5866
73ac5866 fix Reg::changeBit

git-subtree-dir: externals/xbyak
git-subtree-split: 73ac5866099b19bd8063f06434e19b9d7bbc9b8d
2019-04-15 16:18:43 +01:00
Lioncash
105d4ed9e5
A64: Handle half-precision variants of FP->Fixed-point instructions 2019-04-15 08:50:00 -04:00
Merry
d32f648578
Merge pull request #481 from lioncash/alloc
ir/basic_block: Forward declare headers where applicable
2019-04-15 13:04:02 +01:00
Merry
c8446bda2b
Merge pull request #480 from lioncash/info
common/fp/info: Make half-precision info struct functions return correctly sized types
2019-04-15 12:14:30 +01:00
Lioncash
f4d0a09bf4
ir/basic_block: Forward declare headers where applicable
Now that the constructor and destructors have been placed within the cpp
file, we can forward declare the memory pool data structures. Now, a
change to the memory pool code won't ripple across the entirety of the
IR emitter.
2019-04-15 06:00:35 -04:00
Lioncash
db78e2f32c
ir/block: Default ctor and dtor in the cpp file
Prevents potentially inlining allocation code everywhere. While we're at
it, also explicitly delete/default the copy/move constructor/assignment
operators to be explicit about them.
2019-04-15 05:58:36 -04:00
Lioncash
2c2fdb435c
common/fp/info: Make half-precision info struct functions return correctly sized types
While initially done to potentially prevent creating bugs due to C++
having a silly type-promotion mechanism involving types < sizeof(int)
and unsignedness, given that the bulk of these functions' usages
are on exit paths, these can return the correct type to avoid the need
to cast at every usage point.
2019-04-15 04:55:00 -04:00
Merry
973c87445e
Merge pull request #479 from lioncash/rsqrts
A64: Handle half-precision variants of FRSQRTS
2019-04-15 08:28:30 +01:00
Lioncash
189692246d
frontend/ir/microinstruction: Add missing fixed-point opcodes to ReadsFromAndWritesToFPSRCumulativeExceptionBits() 2019-04-15 00:55:49 -04:00
Lioncash
1d3fc42bfe
frontend/ir_emitter: Add half-precision->fixed-point opcodes 2019-04-15 00:55:46 -04:00
Lioncash
6c7de6c9c4
common/fp/op/FPToFixed: Add half-precision specialization of FPToFixed 2019-04-15 00:17:44 -04:00
Lioncash
28e0f4fe59
A64: Implement FRSQRTS' half-precision vector variant 2019-04-14 21:12:54 -04:00
Lioncash
6f7a370cfb
A64: Implement FRSQRTS' half-precision scalar variant
With the necessary machinery in place, we can now handle the
half-precision variant.
2019-04-14 21:12:54 -04:00
Lioncash
793b3b38d4
frontend/ir_emitter: Add half-precision opcode variant of FPVectorRSqrtStepFused 2019-04-14 21:12:54 -04:00
Lioncash
db4d134726
frontend/ir_emitter: Add half-precision opcode variant of FPRSqrtStepFused 2019-04-14 21:12:49 -04:00
Lioncash
cff4394717
common/fp/op/FPRSqrtStepFused: Add half-precision specialization for FPRSqrtStepFused 2019-04-14 20:51:58 -04:00
Merry
eea732febf
Merge pull request #478 from lioncash/stepfused
A64: Handle half-precision variants of FRECPE and FRECPS
2019-04-14 12:40:18 +01:00
Merry
0c62dba214
Merge pull request #477 from lioncash/rsqrt
A64: Handle half-precision variants of FRSQRTE
2019-04-14 11:21:05 +01:00
Lioncash
b67cc72213
A64: Implement half-precision vector variant of FRECPE 2019-04-14 06:14:20 -04:00
Lioncash
4b3f5b8a30
A64: Implement half-precision scalar variant of FRECPE 2019-04-14 06:14:20 -04:00
Lioncash
4519e4641c
A64: Implement half-precision vector variant of FRECPS 2019-04-14 06:14:19 -04:00
Lioncash
abcf1a6e09
A64: Implement half-precision scalar variant of FRECPS 2019-04-14 06:14:19 -04:00
Lioncash
c55db96819
frontend/ir_emitter: Add half-precision opcode for FPVectorRecipEstimate 2019-04-14 06:14:19 -04:00