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Author SHA1 Message Date
MerryMage
3172a4b066 emit_x64_vector: Special-case table_size == 1 in EmitVectorTableLookup 2018-08-19 09:29:41 +01:00
MerryMage
50c589b2b5 emit_x64_vector: SSE4.1 implementation of EmitVectorTableLookup 2018-08-18 22:07:58 +01:00
MerryMage
bc6cf3021f A64: Implement TBL and TBX 2018-08-18 22:00:03 +01:00
MerryMage
8067ab9553 IR: Add VectorTable and VectorTableLookup IR instructions 2018-08-18 21:59:44 +01:00
MerryMage
0e0e839ba0 opcodes: Cleanup opcodes table 
* Remove T:: prefix from types.
* Add another column for a 4th argument.
 2018-08-18 19:39:59 +01:00
Lioncash
8e47d44c4d A64: Implement SDOT and UDOT's vector variant 2018-08-18 15:19:39 +01:00
Lioncash
3a367f341f A64: Implement SADALP and UADALP 
While we're at it we can join the code for SADDLP and UADDLP with these
instructions, since the only difference is we do an accumulate at the
end of the operation.
 2018-08-18 14:24:43 +01:00
Lioncash
5f322a160f A64: Implement SRSHL and URSHL 
Implements both scalar and vector variants.
 2018-08-18 14:23:29 +01:00
Lioncash
a278775c43 ir: Add opcodes for performing rounding left shifts 2018-08-18 14:23:29 +01:00
MerryMage
720efe337e emit_x64_floating_point: Fix smallest normal check in EmitFPMulAdd 2018-08-18 13:49:19 +01:00
Lioncash
fc96d512c9 A64: Implement ISB 
Given we want to ensure that all instructions are fetched again, we can
treat an ISB instruction as a code cache flush.
 2018-08-18 13:30:54 +01:00
Lioncash
2a0317198f A64: Implement FCVTN{2} 2018-08-16 23:01:38 +01:00
Lioncash
f9e084283b A64: Implement FCVTL{2} 2018-08-16 23:01:38 +01:00
Lioncash
9f873410c8 A64: Implement FMAXNM and FMINNM vector variants. 
Currently we can implement these in terms of the scalar IR variants.
 2018-08-16 23:00:42 +01:00
Lioncash
d5d2c36221 A64: Implement FMAXP, FMAXNMP, FMINP, and FMINNMP's vector variants 
We can just implement these in terms of scalars for the time being.
 2018-08-16 15:12:43 +01:00
MerryMage
1474f09d1c emit_x64_vector_floating_point: Correct value of smallest_normal_number 2018-08-16 10:55:02 +01:00
MerryMage
821cabac1b fp/info: Incorrect point_position in FPValue 2018-08-16 10:50:28 +01:00
MerryMage
550d662f0e load_store_exclusive: Define s == t state to be Constraint_NONE 
Downstream (yuzu) mentioned that the instruction:

STXR W9, W9, [X0]

was executed in the program "Crash N-Sane Trilogy".
 2018-08-16 10:04:54 +01:00
MerryMage
0b69381ff4 A64/translate: Allow for unpredictable behaviour to be defined 2018-08-16 09:59:06 +01:00
MerryMage
6d236d459f system: Implement MRS CNTFRQ_EL0 2018-08-16 09:58:34 +01:00
MerryMage
6cbb6fb190 A32/testenv: Add missing headers 2018-08-15 13:48:50 +01:00
MerryMage
67293289bf externals: Update xbyak to v5.67 
Merge commit '1812bd20d08020bfff2ca15e23c0377a21e3cee0'
 2018-08-15 13:31:03 +01:00
MerryMage
1812bd20d0 Squashed 'externals/xbyak/' changes from 2794cde7..671fc805 
671fc805 update test/cybozu
8ca86231 remove mutable in Address
8b93498f add cmpsb/scasb/...
7eb62750 avoid core_sharing_data_cache = 0 for some cloud envrionment
85767e95 support mingw64
59573e6e add PROTECT_RE mode for protect()
71b75f65 fix push(qword[mem])
811f4959 Merge branch 'rsdubtso-master'
8e3cb711 Account for potentially zero 0xb leaf when parsing cache/topology via cpuid
a816249f update version
fe083912 fix to avoid zero division for some virtual machine
f0a8f7fa update version
cac09b7a Merge pull request #62 from mgouicem/master
1f96b5e0 Fixes an error raised by clang < 3.9
c0f885ac Merge pull request #61 from mgouicem/master
bfe2d201 Change default value for n_cores in setCacheHierarchy.
fd587b55 change format and add getter for data_cache_size
80b3c7b9 remove macro
88189609 Merge branch 'mgouicem-master'
e6b79723 Adding queries to get the cpu topology on Intel architectures.
221384f0 vmov* supports [mem]|k|z
c04141ef define XBYAK_NO_OP_NAMES for test
af7f05ee add const for Label

git-subtree-dir: externals/xbyak
git-subtree-split: 671fc805d09d075f48d4625f183ef2e1ef725106
 2018-08-15 13:28:55 +01:00
MerryMage
9a9580290b externals: Document subtrees 2018-08-15 13:28:13 +01:00
Lioncash
714a8405bc A64: Implement SQ{ADD, SUB}, and UQ{ADD, SUB}'s vector variants 
Currently we implement these in terms of the scalar variants. Falling
back to the interpreter is slow enough to make it more effective than
doing that.
 2018-08-14 08:48:06 +01:00
Lioncash
8cab459661 A64: Implement UQADD/UQSUB's scalar variants 2018-08-14 08:48:06 +01:00
Lioncash
18a8151684 ir: Add opcodes for unsigned saturating add and subtract 2018-08-14 08:48:06 +01:00
Lioncash
a5660eec11 x64/reg_alloc: Use type alias for array returned by GetArgumentInfo() 
This way if the number ever changes, we don't need to change the type in
other places.
 2018-08-13 21:55:40 +01:00
Lioncash
29489b598e ir/value: Use type alias CoprocessorInfo for std::array<u8, 8> 
Provides a more descriptive label for the interface, and avoids the need
to hardcode the array size in multiple places.
 2018-08-13 21:55:14 +01:00
MerryMage
e23ba26d88 status_register_access: Add support for bits 0 and 1 of mask to MSR 2018-08-11 21:26:15 +01:00
MerryMage
55190bd792 fuzz_with_unicorn: Split utility functions into fuzz_util 2018-08-11 20:51:30 +01:00
MerryMage
23b049d2fe A32/translate/load_store: Correct detection of writeback 2018-08-11 20:51:30 +01:00
MerryMage
7ec9f15636 A32/translate: Add TranslateSingleInstruction 2018-08-11 20:51:30 +01:00
MerryMage
efeecb46ff A32/ir_emitter: Bug fix: IREmitter::ExceptionRaised using incorrect opcode 2018-08-11 18:18:29 +01:00
MerryMage
08d1d19805 A32/decoders: Split instruction list into include file 2018-08-11 18:18:29 +01:00
MerryMage
2d929cc3b3 tests: Refactor unicorn_emu to allow for A32 unicorn 2018-08-11 18:18:29 +01:00
MerryMage
f672368ac3 microinstruction: Improve assert messages 2018-08-11 10:43:40 +01:00
MerryMage
7ebff50d46 emit_x64_vector: EmitVectorNarrow16: AVX512 implementation 2018-08-10 21:57:58 +01:00
MerryMage
edce230ebe emit_x64_vector: EmitVectorNarrow32: prefer pblendw to loading constant 2018-08-10 21:57:37 +01:00
MerryMage
0118ee04f9 emit_x64_vector: packusdw is SSE4.1 2018-08-10 11:09:49 +01:00
MerryMage
4f96c63025 emit_x64_vector_floating_point: Simplify FPVector{Min,Max} 2018-08-03 11:48:17 +01:00
MerryMage
e15fdfe696 emit_x64_vector_floating_point: Simplify Get*Vector functions 2018-08-03 11:48:17 +01:00
MerryMage
734a00b608 emit_x64_floating_point: Remove EmitProcessNaNs 2018-08-03 11:48:17 +01:00
MerryMage
fd45191e44 devirtualize: Replace DEVIRT macro with function template 2018-08-03 09:09:29 +01:00
MerryMage
67ba5d0072 fuzz_with_unicorn: Remove FCVT_float from ignore list 2018-08-03 08:18:40 +01:00
Lioncash
66e6dd1cab a32_emit_x64: std::move A32::UserConfig in the constructor 
This avoids a few redundant atomic increments and decrements,
considering the UserConfig instance contains a std::array of
std::shared_ptr<Coprocessor> instances.
 2018-08-03 08:12:36 +01:00
MerryMage
b4890b6f32 emit_x64_floating_point: Use EmitPostProcessNaNs in EmitFPMulX 2018-08-03 07:31:51 +01:00
MerryMage
18b29435f7 emit_x64_floating_point: Remove unnecessary DenormalsAreZero from EmitFPSingleToDouble and EmitFPDoubleToSingle 2018-08-02 21:12:24 +01:00
MerryMage
df1f81f998 emit_x64_floating_point: Simplify EmitFP{Min,Max}{,Numeric}{32,64} 2018-08-02 21:09:35 +01:00
MerryMage
21fb1c3a7f emit_x64_floating_point: Reduce NaN processing overhead 2018-08-02 17:17:23 +01:00