MerryMage
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3fffeadf0d
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emit_x64_vector: EmitOneArgumentFallback
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2018-02-11 11:59:43 +00:00 |
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MerryMage
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4df6c424df
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Forward declare IR::Opcode and IR::Type where possible
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2018-02-11 11:52:44 +00:00 |
|
MerryMage
|
09632954d7
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A64: Implement CNT
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2018-02-11 11:52:44 +00:00 |
|
MerryMage
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c2c9ea85a5
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IR: Implement VectorPopulationCount
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2018-02-11 11:52:44 +00:00 |
|
MerryMage
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0996d4fd2e
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A64: Implement MLS (vector)
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2018-02-11 11:04:46 +00:00 |
|
MerryMage
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5319f6af95
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A64: Implement MLA (vector)
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2018-02-11 11:00:16 +00:00 |
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MerryMage
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17519df3e8
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emit_x64_vector: Add SSE4.1 implementation for EmitVectorMultiply64
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2018-02-11 10:47:22 +00:00 |
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MerryMage
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eac6a56a4b
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emit_x64_vector: More explicit lambda decay
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2018-02-11 10:47:00 +00:00 |
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MerryMage
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727b1b0b51
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A64: Implement MUL (vector)
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2018-02-11 10:18:47 +00:00 |
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MerryMage
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80fce9c4b9
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IR: Implement VectorMultiply
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2018-02-11 10:18:29 +00:00 |
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MerryMage
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cb65a26da2
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emit_x64_vector: Order alphabetically
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2018-02-11 09:41:37 +00:00 |
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MerryMage
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2b968981a1
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A64: Implement STR (register, SIMD&FP), LDR (register, SIMD&FP)
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2018-02-11 01:06:26 +00:00 |
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MerryMage
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7681159811
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decoder/a64: Don't rearrange unrelated decoders
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2018-02-11 00:43:33 +00:00 |
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MerryMage
|
56fe848e4e
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A64: Implement SUB (vector)
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2018-02-10 23:58:33 +00:00 |
|
MerryMage
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b429efa081
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A64: Implement SIMD instruction SSRA, vector variant
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2018-02-10 23:30:00 +00:00 |
|
MerryMage
|
0a96a437cb
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A64: Implement SIMD instruction SSHR, vector variant
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2018-02-10 23:28:05 +00:00 |
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MerryMage
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a5299d0be5
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IR: Implement VectorArithmeticShiftRight
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2018-02-10 23:27:46 +00:00 |
|
MerryMage
|
8e8068cfaf
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impl: Improve Vpart setter
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2018-02-10 17:05:52 +00:00 |
|
MerryMage
|
5ffa84f41d
|
A64: Implement SIMD instructions XTN, XTN2
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2018-02-10 17:01:33 +00:00 |
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MerryMage
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dc9785bdcd
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IR: Implement VectorNarrow
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2018-02-10 17:01:33 +00:00 |
|
MerryMage
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ebc594385c
|
constant_pool: Allow for 128-bit constants
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2018-02-10 16:36:00 +00:00 |
|
MerryMage
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8e23683b63
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emit_x64_vector: Add SSE4.1 implementations for VectorZeroExtend
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2018-02-10 16:24:43 +00:00 |
|
MerryMage
|
d9f803924e
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IR: Implement VectorSub
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2018-02-10 11:25:50 +00:00 |
|
MerryMage
|
c01bbbd09d
|
A64: Implement SIMD instruction USRA, vector variant
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2018-02-10 11:12:54 +00:00 |
|
MerryMage
|
9e80f94b5f
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A64: Implement SIMD instruction USHR, vector variant
|
2018-02-10 11:05:58 +00:00 |
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MerryMage
|
e6a0a4d8ce
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IR: Implement VectorLogicalShiftRight
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2018-02-10 11:05:22 +00:00 |
|
MerryMage
|
60ddaa8f38
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A64: Implement SIMD instructions USHLL, USHLL2
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2018-02-10 10:35:14 +00:00 |
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MerryMage
|
670b47149e
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IR: Implement VectorZeroExtend
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2018-02-10 10:35:14 +00:00 |
|
MerryMage
|
7ec12cbade
|
IR: Vector instructions now take esize argument in emitter
|
2018-02-10 10:18:10 +00:00 |
|
MerryMage
|
b219105b75
|
A64: Implement SIMD instruction SHL
|
2018-02-10 09:49:55 +00:00 |
|
MerryMage
|
570911e693
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IR: Implement VectorLogicalShiftLeft{8,16,32,64}
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2018-02-10 09:31:54 +00:00 |
|
MerryMage
|
e03a9fed98
|
opcodes: Sort vector IR opcodes alphabetically
|
2018-02-10 09:15:01 +00:00 |
|
MerryMage
|
406c071008
|
block_of_code: Increase constant pool size
|
2018-02-09 16:04:56 +00:00 |
|
MerryMage
|
9be412bbc2
|
devirtualize: MinGW uses Intanium MFP ABI
|
2018-02-09 16:04:48 +00:00 |
|
MerryMage
|
7a0fdf01bb
|
callback: Properly handle calls with return pointers and simplify interface
|
2018-02-09 16:02:57 +00:00 |
|
FernandoS27
|
dee211c4df
|
Implemented BSL, BIC, BIT and BIF vector instructions
|
2018-02-09 13:28:16 +00:00 |
|
MerryMage
|
15da38d3aa
|
devirtualize: Handle Windows ABI
|
2018-02-09 11:19:40 +00:00 |
|
MerryMage
|
41ae12263d
|
travis: Switch to yuzu-emu's unicorn repository
|
2018-02-08 19:48:04 +00:00 |
|
MerryMage
|
83a762eee7
|
fuzz_arm: Use SCOPE_FAIL
|
2018-02-08 02:14:42 +00:00 |
|
MerryMage
|
b0991ee46f
|
A32/decoder/arm: bug: Correct bitstring for SRS
|
2018-02-08 02:05:49 +00:00 |
|
MerryMage
|
43035fd064
|
devirtualize: Devirtualize Itanium ABI MFPs at runtime
|
2018-02-07 12:25:45 +00:00 |
|
MerryMage
|
36ec1d09cf
|
cast_util: Add BitCast and BitCastPointee
|
2018-02-07 12:25:45 +00:00 |
|
Lioncash
|
1ee5b2e352
|
A64: Move SDIV and UDIV out of data_processing_multiply.cpp
|
2018-02-07 12:07:09 +00:00 |
|
Lioncash
|
25e7c94995
|
A64: Implement ZIP1
|
2018-02-07 12:06:49 +00:00 |
|
FernandoS27
|
c882e6819d
|
Implemented UMULH and SMULH instructions
|
2018-02-06 23:59:24 +00:00 |
|
MerryMage
|
32be42c68e
|
A64: Implement MOVI, MVNI, ORR (vector, immediate), BIC (vector, immediate)
There wasn't a clean way to seperate these instructions out.
|
2018-02-06 23:29:18 +00:00 |
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MerryMage
|
b6775f1282
|
impl: Add AdvSIMDExpandImm
|
2018-02-06 23:04:23 +00:00 |
|
MerryMage
|
023c2c9818
|
A64: Implement SUB (vector), scalar variant
|
2018-02-06 22:12:39 +00:00 |
|
MerryMage
|
b544b8f4b1
|
A64: Implement ADD (vector), scalar variant
|
2018-02-06 22:09:39 +00:00 |
|
MerryMage
|
63d3a1cc1c
|
A64: Reorganize decoder tables (some vector entries were grouped with scalar entries)
|
2018-02-06 18:30:36 +00:00 |
|