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Author SHA1 Message Date
Lioncash
4798a40908 reg_alloc: std::move RegAlloc's function argument 2018-01-27 02:52:59 +00:00
Lioncash
c40e7acc8e General: Add missing override specifiers 2018-01-27 02:46:04 +00:00
MerryMage
e111309aba EmitZeroExtendLongToQuad: Do not rely on register allocator to zero extend 64->128 2018-01-27 02:00:49 +00:00
MerryMage
a1018a4eea a64_get_set_elimination_pass: Simplify algorithm 2018-01-27 02:00:49 +00:00
MerryMage
ac1f4d3d5d a64_emit_x64: bug: x64 sign-extends 32-bit immediates 2018-01-27 00:38:43 +00:00
MerryMage
9232be5553 ir_opt: Add A64 Get/Set Elimination Pass 2018-01-27 00:38:43 +00:00
MerryMage
39b7625e9d ir_emitter: Allow the insertion point for new instructions to be set 2018-01-27 00:38:43 +00:00
MerryMage
68c5399607 {a32,a64}_interface: Predict entrypoint 2018-01-27 00:38:42 +00:00
Lioncash
dbddb4858a A64: Implement EXTR 2018-01-26 22:07:48 +00:00
MerryMage
0dc584a62d externals: Update xbyak to v5.601 
Merge commit '43330ec3ba6dae3829675874258bdd717d0f3f19'
 2018-01-26 18:39:45 +00:00
MerryMage
43330ec3ba Squashed 'externals/xbyak/' changes from d512551e..2794cde7 
2794cde7 add xword, yword, etc. in Xbyak::util
fb9c04e4 fix document for vfpclassps
a51be78b fix test dependency
04fdfb1e update version
e6354f8b add vgf2p8mulb
09a12642 add gf2p8affineqb
d171ba0e add gf2p8affineinvqb
457f4fd0 add vpshufbitqmb
5af0ba39 add vpexpand{b,w}
e450f965 vpopcnt{d,q} supports ptr_b
48499eb1 add vpdpbusd(s), vpdpwssd(s)
9c745109 add vpdpbusd, vpdpbusds
0e1a11b4 add vpopcnt{b,w,d,q}
9acfc132 add vpshrd(v){w,d,q}
ac8de850 add vpshld(v){w,d,q}
f181c259 add vcompressb, vcompressw
5a402477 vpclmulqdq supports AVX-512
9e16b40b vaes* supports AVX-512
7fde08e0 add flags for intel's manual 319433-030.pdf
c5da3778 add test of v4fmaddps, vp4dpwssd, etc.
e4fc9d8a fix mpx encoding
d0b2fb62 add bnd(0xf2) prefix for MPX
f12b5678 use db for array
cd74ab44 remove bat file

git-subtree-dir: externals/xbyak
git-subtree-split: 2794cde79eb71e86490061cac9622ad0067b8d15
 2018-01-26 18:39:45 +00:00
MerryMage
bda9148e71 A64: Implement LDP (SIMD&FP) and STP (SIMD&FP) 2018-01-26 18:39:19 +00:00
MerryMage
e789d8ff53 a64_jitstate: Have 128-bit wide spills 2018-01-26 18:38:31 +00:00
MerryMage
0c1c82a937 IR: Implement IR instructions A64{Get,Set}S 2018-01-26 18:38:30 +00:00
MerryMage
ef6b4f20ca a64_emit_x64: Use xword from Xbyak::util 2018-01-26 18:38:30 +00:00
Lioncash
8c013e7928 General: Convert multiple namespace specifiers to nested namespace specifiers where applicable 
Makes namespacing a little less noisy
 2018-01-26 17:06:48 +00:00
Lioncash
792cb91753 A64: Zero upper 64 bits in ORN if using the 64-bit variant 
Resolves a TODO
 2018-01-26 17:06:26 +00:00
Lioncash
07930f0253 unicorn: Display EC and ISS separately beside the full ESR value 
Makes it a little nicer to pick out the exception class details at a glance
 2018-01-26 12:31:43 +00:00
Lioncash
e99cbcf4e3 unicorn: Use static_cast instead of reinterpret_cast 
It's well-defined to cast from void* back to the original pointer type.
 2018-01-26 12:31:33 +00:00
MerryMage
a3af4dd218 load_store_register_unprivileged: bug: LDTRSW 2018-01-26 02:03:16 +00:00
MerryMage
06bea0ceaa A64: Implement CMEQ (register, vector) 2018-01-26 01:52:42 +00:00
MerryMage
f7e8a2259a IR: Implement IR instructions VectorEqual{8,16,32,64,128} 2018-01-26 01:52:06 +00:00
MerryMage
f833a17906 reg_alloc: Use std::exchange 2018-01-26 01:51:04 +00:00
Fernando Sahmkow
5ffd11d140 A64: Implemented EOR (vector), ORR (vector, register) and ORN (vector) Instructions (#142) 2018-01-26 00:57:56 +00:00
Lioncash
fc82109071 unicorn_load: Minor Windows-related changes 
- Add missing include
- Fix a potential compilation issue where the constructor wouldn't be able to execute, as it would be private.
 2018-01-26 00:52:46 +00:00
MerryMage
d08b738662 tests/A64: Test memory writes 2018-01-25 23:56:57 +00:00
MerryMage
d99c99aabb microinstruction: Missed A64{Read,Write}Memory128 from opcode information 2018-01-25 23:56:14 +00:00
MerryMage
85034beaac emit_x64_packed: EmitPackedSubU16 modified xmm_b wasn't writeable 
For CPUs that didn't support SSE4.1, this was a bug.
 2018-01-25 18:41:53 +00:00
Lioncash
1ffe4e03d9 tests: Fix truncation in GetFpcr() 2018-01-25 18:26:32 +00:00
James Rowe
0cc1bce1a8 Fixup: Xn|SP are 64 bit addresses encoded in the Rn field 2018-01-25 17:46:14 +00:00
James Rowe
76aaa84687 A64: Fix bugs and address review comments 2018-01-25 17:46:14 +00:00
James Rowe
7825ae3a4f Add missing returns 2018-01-25 17:46:14 +00:00
James Rowe
ddb5b3469d A64: Implement Load/Store register (unprivileged) 2018-01-25 17:46:14 +00:00
MerryMage
7f3a790de5 fixup: travis: Test with disabled CPU feature detection 2018-01-24 19:42:54 +00:00
Lioncash
850337e434 CMakeLists: Add opcodes.inc to the source file list 
Allows the file to show up nicely within IDEs
 2018-01-24 19:42:02 +00:00
MerryMage
7d389fb5f8 travis: Test with disabled CPU feature detection 
Ensure that fallbacks are working correctly.
 2018-01-24 19:22:45 +00:00
MerryMage
314e020992 IR: Add IR instruction VectorZeroUpper 2018-01-24 17:11:13 +00:00
MerryMage
8ce3e0518a a64_emit_x64: bug: EmitA64WriteMemory128 should write not read 2018-01-24 17:10:44 +00:00
FernandoS27
d1664096f5 Implemented SDIV and UDIV instructions 2018-01-24 17:09:00 +00:00
MerryMage
8873d17db2 A64: Implement LDR/STR (immediate, SIMD&FP) 2018-01-24 16:28:18 +00:00
MerryMage
7f5ce36368 IR: Add IR instructions A64Memory{Read,Write}128 
Add the Windows ABI implementation
 2018-01-24 16:28:18 +00:00
MerryMage
d6589fe3ee IR: Add IR instructions A64Memory{Read,Write}128 
This implementation only works on macOS and Linux.
 2018-01-24 16:18:58 +00:00
MerryMage
5421c90216 IR: Add IR instruction VectorGetElement{8,16,32,64} 2018-01-24 16:18:58 +00:00
MerryMage
3932d6d695 IR: Add IR instruction ZeroExtendToQuad 2018-01-24 16:18:58 +00:00
MerryMage
264c446e54 block_of_code: Add ABI_RETURN2 2018-01-24 16:18:58 +00:00
MerryMage
ed63cc7ae9 interface: Move Vector typedef to config.h 2018-01-24 16:18:58 +00:00
MerryMage
ef81c2bcfc bit_util: bug: Infinite loop in HighestSetBit 2018-01-24 16:18:58 +00:00
MerryMage
1db423b2ad A64: Implement DUP (general) 2018-01-24 12:01:26 +00:00
MerryMage
6f1c44e311 IR: Implement Vector{Lower,}Broadcast{8,16,32,64} 2018-01-24 12:01:26 +00:00
Lioncash
cdb588dab5 General: Default constructors and destructors where applicable 2018-01-24 09:07:22 +00:00