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Author SHA1 Message Date
MerryMage
5573953428 Merge branch 'global_monitor' 2018-07-07 22:52:50 +01:00
Lioncash
0ae8540234 simd_two_register_misc: Utilize FPVectorAbs in FABS implementations 
Since we already have opcodes introduced to implement FACGE and FACGT,
we can reutilize it for the FABS implementations.
 2018-07-07 21:42:42 +01:00
Lioncash
c566307b87 ir: Extend FPVectorAbs opcode to also handle 16-bit elements for FP16 2018-07-07 21:42:42 +01:00
Lioncash
9760ea1f93 A64: Implement FACGE's vector single/double precision variants 2018-07-07 14:49:47 +01:00
Lioncash
488ebdb793 A64: Implement FACGT's vector single/double precision variants 2018-07-07 14:49:47 +01:00
Lioncash
f769be89dc ir: Add opcodes for performing vector absolute floating-point values 
This will be usable for implementing FACGE and FACGT
 2018-07-07 14:49:47 +01:00
Lioncash
402032d107 emit_x64_vector: Deduplicate a bit of code in EmitVectorSetElement{8, 32, 64} functions 
Given both branches are the same, we can hoist out the common code.
 2018-07-07 14:49:14 +01:00
Lioncash
f7d11baa1c A64: Implement load/store single structure instructions 
Implements LD{1, 2, 3, 4}, LD{1, 2, 3, 4}R, and ST{1, 2, 3, 4} single
structure variants.
 2018-07-06 23:01:35 +01:00
Lioncash
c4be14d5bf emit_x64_vector: Deduplicate a bit of code within EmitVectorGetElement8() 
Given both branches use the same destination register size, we can hoist
the common code out.
 2018-07-06 23:00:58 +01:00
MerryMage
a6432b7e5b A64: Add ClearExclusiveState method 2018-07-04 00:05:14 +01:00
MerryMage
86cd8c9a69 tests: Add print_info program 
Eases debugging by printing out dynarmic IR for a given A64 instruction, along with
information about what instruction dynarmic thinks it is.

Also prints an LLVM disassembly of the instruction.
 2018-06-27 21:23:14 +01:00
MerryMage
f4e824d396 ir/basic_block: Add missing U16 immediate type to DumpBlock 2018-06-27 21:23:05 +01:00
MerryMage
89a2b80c1f llvm_disassemble: Allow disassembly of invalid AArch64 instructions 2018-06-27 21:22:53 +01:00
Lioncash
11941f70e1 externals: Update catch to v2.2.3 
Keeps the unit-testing library up to date.
 2018-06-09 22:33:57 +01:00
Lioncash
96c4b1e793 A64: Implement FABD's scalar single/double precision variant 2018-06-09 10:28:45 +01:00
Lioncash
2b0df59e7b A64: Implement FABD's vector single/double precision variant 2018-06-09 10:28:45 +01:00
Lioncash
cfeda05286 ir: Add opcode for performing FP vector absolute differences 2018-06-09 10:28:45 +01:00
MerryMage
c15c9e7049 A64: Implement FNMSUB 2018-06-08 15:23:44 +01:00
MerryMage
6ad682c1c4 A64: Implement FNMADD 2018-06-08 15:23:42 +01:00
MerryMage
a0093c031f A64: Implement FMSUB 2018-06-08 15:23:40 +01:00
MerryMage
4a2c374500 A64: Implement FMADD 2018-06-08 15:23:37 +01:00
MerryMage
f05cb06244 IR: Implement FPMulAdd 2018-06-08 15:23:35 +01:00
Lioncash
0299f05698 A64: Implement FCMGT, FCMGE (register) vector double and single precision variants 2018-06-05 17:21:35 +01:00
Lioncash
7454c8a93a A64: Implement FCMGT, FCMGE, FCMLE, FCMLT (zero) vector double and single precision variants. 2018-06-05 17:21:35 +01:00
Lioncash
21a38854e5 ir: Add opcode for floating-point GE and GT comparisons 
The rest of the comparisons can be implemented in terms of these two
 2018-06-05 17:21:35 +01:00
MerryMage
614840940e a64_emit_x64: Clear exclusive state in EmitA64CallSupervisor 
The kernel would have to execute an ERET instruction to return to
userland; this clears exclusive state.
 2018-06-05 13:05:41 +01:00
MerryMage
f915f0860c Implement global exclusive monitor 2018-06-05 12:27:37 +01:00
MerryMage
169c1a07ca a64_emit_x64: Simplify EmitExclusiveWrite 2018-06-05 12:26:05 +01:00
MerryMage
7e31103cf8 CMakeLists: Add missing files 2018-06-05 12:25:16 +01:00
Lioncash
9d27e78989 A64: Implement FCMEQ (zero)'s vector single and double precision variant 2018-06-03 21:49:06 +01:00
Lioncash
0ca366b94e A64: Implement FCMEQ (register)'s vector single and double precision variant 2018-06-03 21:49:06 +01:00
Lioncash
239d2243c0 ir: Add opcodes for floating-point vector equalities 2018-06-03 21:49:06 +01:00
Lioncash
7dc6b5abb3 fuzz_with_unicorn: Make float_numbers in floating-point tests constexpr 
Given this is just a lookup table, this can be made immutable.
 2018-06-02 16:47:13 +01:00
Lioncash
06c1cf6721 emit_x64_vector: Vectorize fallback case in EmitVectorMultiply64() 
Gets rid of the need to perform a fallback.
 2018-05-26 21:33:46 +01:00
Lioncash
b747b67354 emit_x64_vector: Add break to final case in EmitVectorRoundingHalvingAddUnsigned() 
This doesn't alter behavior but does make the code better if anything
else is ever added to this function in the future.
 2018-05-26 21:25:14 +01:00
Lioncash
c623a94a4d A64: Implement SRHADD and URHADD 2018-05-26 11:48:56 +01:00
Lioncash
2652e92928 ir: Add opcodes for performing rounding halving adds 2018-05-26 11:48:56 +01:00
Lioncash
990a569b7a emit_x64_vector: Simplify AVX-512 codepath in EmitVectorMultiply64 
I realized I introduced a helper for simple AVX operation emitting, so
use that instead of writing it all out long-form.
 2018-05-23 08:02:12 +01:00
Lioncash
66c5d8fb06 A64: Implement UMLAL{2}, UMLSL{2}, and UMULL{2} 
Now that we have the helper function set up for the signed variants, we
can also modify it to be used with the unigned ones by performing a zero
extension instead of a sign extension.
 2018-05-23 07:58:41 +01:00
Lioncash
5f53fd2be8 A64: Implement SMLSL{2} 2018-05-23 07:58:41 +01:00
Lioncash
b6ed3f9c66 A64: Implement SMLAL{2} 2018-05-23 07:58:41 +01:00
Lioncash
2bfe1ce838 A64: Implement SMULL{2} 2018-05-23 07:58:41 +01:00
Lioncash
be453b0e1c fuzz_with_unicorn: Remove exclusion of FMOV (imm) for FP-16 floats 
Qemu, or rather, Unicorn now supports FP-16, since I backported support
for the recent changes to mainline Qemu relating to FP-16 support.
 2018-05-19 12:25:43 +01:00
Lioncash
1f00e53b54 A64: Implement SABAL/SABAL2 and SABDL/SABDL2 
Now that we have a helper function for the unsigned variants, we can
modify it to also be usable with the signed variants.
 2018-05-14 23:10:01 +01:00
Lioncash
de3b545e57 A64: Implement UABAL/UABAL2 2018-05-14 23:10:01 +01:00
Lioncash
e1ab52c057 A64: Implement UABDL/UABDL2 2018-05-14 23:10:01 +01:00
Lioncash
7cd0ff18bf emit_x64_vector: Emit VPMULLQ in EmitVectorMultiply64 on AVX-512{DQ, VL} capable CPUs 
Shortens code-gen down to a single instruction in the 64-bit path.
 2018-05-14 23:09:31 +01:00
Lioncash
f8f4f9abb4 A64: Implement LDR (literal, SIMD&FP) 2018-05-14 23:09:15 +01:00
Lioncash
b00f6d1044 Correct typo in DataCacheOperation enum 
Fixes a typo for the InvalidateByVAToPoC enum entry. Given yuzu is the
only known user of 64-bit mode and it doesn't use this value, we can get
away with changing this.
 2018-05-14 15:39:08 +01:00
Lioncash
ced64f7dda A64: Implement FABS' half-precision variant 2018-05-12 11:17:46 +01:00