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1213 Commits

Author SHA1 Message Date
MerryMage
57604d2ea8 a32_emit_x64: Assert that memory layout assumption in EmitA32GetCpsr is valid 2018-07-26 19:26:01 +01:00
Lioncash
945fa48667 A64: Implement PMUL 2018-07-26 16:16:30 +01:00
Lioncash
656a4042a2 ir: Add opcode for performing polynomial multiplication 2018-07-26 16:16:30 +01:00
MerryMage
05143df9d8 A64: Implement FCVT{N,M,A,P}{U,S} (vector), FCVTZU (vector, integer), single/double variant 2018-07-26 12:48:36 +01:00
MerryMage
34ce767a00 A64: Implement FCVTZS (vector, integer), single/double variant 2018-07-26 12:48:36 +01:00
MerryMage
0f9bc2d391 IR: Implement FPVectorTo{Signed,Unsigned}Fixed 2018-07-26 12:48:36 +01:00
MerryMage
0189e4454a fp/info: Replace constant value generators with FPValue 
Instead of having multiple different functions we can just have one.
 2018-07-26 11:35:35 +01:00
MerryMage
db165684c0 emit_x64_vector_floating_point: AVX implementation of FPVector{Max,Min} 2018-07-26 10:10:47 +01:00
MerryMage
31148bdb42 emit_x64_vector_floating_point: Remove unnecessary double jump in HandleNaNs 2018-07-26 09:42:34 +01:00
Lioncash
4c3ca51e86 A64: Implement FMAX's vector single and double precision variants 2018-07-26 09:32:02 +01:00
Lioncash
bf0f21cc12 A64: Implement FMIN's vector single and double precision variants 2018-07-26 09:32:02 +01:00
MerryMage
76f0ca04d6 IR: Implement FPVector{Max,Min} 2018-07-26 09:31:56 +01:00
MerryMage
6c37c311de FPRecipEstimate: Move offset out of function 
MSVC has weird lambda capturing rules.
 2018-07-25 19:22:35 +01:00
MerryMage
59546f3c60 microinstruction: Update ReadsFromAndWritesToFPSRCumulativeExceptionBits 2018-07-25 19:17:07 +01:00
MerryMage
3f6b03a06b A64: Implement FRECPS, vector/scalar single/double variants 2018-07-25 19:14:23 +01:00
MerryMage
2d2ca5ebc1 IR: Implement FPRecipStepFused, FPVectorRecipStepFused 2018-07-25 19:14:23 +01:00
MerryMage
5cb9f1dab2 A64: Implement FRECPE, vector single/double variant 2018-07-25 18:55:58 +01:00
MerryMage
c5a14ab21b IR: Implement FPVectorRecipEstimate 2018-07-25 18:55:40 +01:00
MerryMage
56f8a0b172 A64: Implement FRECPE, scalar single/double variant 2018-07-25 18:47:45 +01:00
MerryMage
fde69b4d36 IR: Implement FPRecipEstimate 2018-07-25 18:47:22 +01:00
MerryMage
186e52ca50 IR: Implement FPRecipEstimate 2018-07-25 18:36:40 +01:00
MerryMage
cf2e1aed96 fp: Change FPUnpacked to a normalized representation 
Having a known position for the highest set bit makes writing algorithms easier
 2018-07-25 17:42:36 +01:00
MerryMage
041b7d5e17 block_of_code: Add ABI_PARAMS array 2018-07-25 13:59:14 +01:00
MerryMage
2a2371c7a5 A64: Implement MLA, MLS (by element), vector single/double variant 2018-07-25 13:58:34 +01:00
MerryMage
78c640ad9e A64: Implement FMLS (vector), single/double variant 2018-07-25 13:45:02 +01:00
MerryMage
b6b6993884 emit_x64_vector_floating_point: Specify NanHandler::function_type explicitly 
MSVC doesn't like dealing with auto return types
 2018-07-25 13:38:32 +01:00
MerryMage
4b9d12a585 emit_x64_vector_floating_point: ChooseOnFsize arguments maybe_unused 2018-07-25 13:27:31 +01:00
MerryMage
b1e3616de2 IR: Implement FPVectorNeg 2018-07-25 13:25:35 +01:00
MerryMage
4343612ec4 A64: Implement FMLA (vector), single/double variant 2018-07-25 13:20:07 +01:00
MerryMage
93eeb25fac IR: Implement FPVectorMulAdd 2018-07-25 13:19:48 +01:00
MerryMage
57e5c7e7a5 emit_x64_vector_floating_point: Standardize naming scheme 2018-07-25 12:08:00 +01:00
MerryMage
bcb9e4106d emit_x64_floating_point: Simplify indexers 2018-07-25 12:05:41 +01:00
MerryMage
83aa5854b6 emit_x64_vector_floating_point: Simplify EmitVectorOperation* 2018-07-25 11:34:22 +01:00
MerryMage
f4087c81e5 mp: rename mp.h to mp/function_info.h 2018-07-25 11:28:36 +01:00
MerryMage
18640903ac emit_x64_vector: Slightly improve ArithmeticShiftRightByte 2018-07-25 09:33:02 +01:00
MerryMage
e048441d44 emit_x64_vector: Simplify VectorShuffleImpl 2018-07-24 22:46:45 +01:00
MerryMage
ff025e88d0 IR: Implement A64OrQC 2018-07-24 19:04:40 +01:00
MerryMage
6fac68dd1d A64: Implement UQSHRN, UQRSHRN (vector) 2018-07-24 18:54:28 +01:00
MerryMage
5a8d9c3487 emit_x64_vector: -0x80000000 isn't -0x80000000 2018-07-24 18:45:45 +01:00
MerryMage
759289ec5c A64: Implement UQXTN (vector) 2018-07-24 18:31:32 +01:00
MerryMage
2a96281587 emit_x64_vector: Fix non-SSE4.1 saturated narrowing reconstruction comparison 
Allows non-SSE4.1 to produce the correct FPSR.QC flag
 2018-07-24 18:17:14 +01:00
MerryMage
0682353626 A64: Implement SQXTN (vector) 2018-07-24 17:59:14 +01:00
MerryMage
6c5229ed47 emit_x64_vector: packusdw reqiures SSE4.1 
In EmitVectorSignedSaturatedNarrowToUnsigned32.
 2018-07-24 17:32:00 +01:00
MerryMage
158d9b16f0 A64: Implement SQSHRUN, SQRSHRUN (vector) 2018-07-24 17:20:49 +01:00
MerryMage
f886013526 simd_shift_by_immediate: Simplify ShiftRight 2018-07-24 16:38:51 +01:00
MerryMage
d9b59c69de A64: Implement SQXTUN 2018-07-24 16:32:10 +01:00
MerryMage
50fe28b976 microinstruction: Reorganize FPSCR related instruction queries 2018-07-24 12:13:18 +01:00
Lioncash
d9d036acc9 microinstruction: Add missing FP scalar opcodes to ReadsFromFPSCR() and WritesToFPSCR() 
These were forgotten when the opcodes were added.
 2018-07-24 11:55:15 +01:00
Lioncash
db96163637 u128: Make Bit() a const-qualified member function 
This function doesn't modify the struct members, so it can be made
const.
 2018-07-24 09:15:44 +01:00
MerryMage
f7052ae04d A64: Implement FRSQRTS (vector), single/double variant 2018-07-23 22:58:52 +01:00