Lioncash
6f03fddee5
A64: system: Use an enum class for MRS/MSR register encodings
...
Reduces the need to manually write out the register bit encodings repeatedly.
2018-03-29 12:44:37 +01:00
MerryMage
12a102046c
emit_X64_floating_point: Near jmp to end instead of short jmp
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Jump destination can be further than what can be reached in a short
jump under some FPCR options.
2018-03-27 08:21:21 +01:00
Lioncash
6278f83560
emit_x64_vector: Fix typo in VectorShuffleImpl
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This is supposed to be pshufd, not pshufw (which only allows a 64-bit operand)
2018-03-23 19:51:09 +00:00
Lioncash
25a0204203
A64: Implement REV64
2018-03-23 17:34:59 +00:00
Lioncash
aa92e33194
bit_util: Do nothing in RotateRight if the rotation amount is zero
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Without this sanitizing it's possible to perform a shift with a shift
amount that's the same size as the type being shifted. This actually
occurs when decoding ORR variants.
We could get fancier here and make this branchless, but we don't
really use RotateRight in any performance intensive areas.
2018-03-21 19:30:02 +00:00
Lioncash
e537985584
A64: Implement REV32 (vector)
2018-03-21 15:40:03 +00:00
Lioncash
f62a258945
ir: Add IR opcodes for emitting vector shuffles
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This uses the ARM terminology for sizes (Halfword -> 2 bytes, Word -> 4 bytes)
as opposed to the x86 terminology of (Word -> 2 bytes, Double word -> 4 bytes)
2018-03-21 15:40:03 +00:00
Lioncash
36ac6ec102
emit_x64_vector_floating_point: Fix out of bounds array access in EmitVectorOperation64
2018-03-21 15:39:44 +00:00
Lioncash
20a59a9721
A64: Implement REV16 (vector)
2018-03-16 18:01:33 +00:00
Lioncash
b2f7bb0263
CMakeLists: Add fp_util, macro_util and math_util headers
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Allows the headers to show up within IDEs
2018-03-13 23:21:20 +00:00
Lioncash
fd21b58c3d
A64: Implement EOR3 and BCAX
2018-03-13 23:20:58 +00:00
Lioncash
a48c0bbf9c
travis: Use yuzu's unicorn fork
2018-03-13 23:20:58 +00:00
Lioncash
59e62e089e
externals: Update catch to v2.2.1
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Keeps the testing library up to date
2018-03-12 18:03:45 +00:00
MerryMage
6b4c6b06a9
impl: Update PC when raising exception
2018-02-21 21:02:42 +00:00
MerryMage
7a1313aa24
A64: Implement FDIV (vector)
2018-02-21 15:03:36 +00:00
MerryMage
b2d781da3a
system: Raise exception for YIELD, WFE, WFI, SEV, SEVL
2018-02-20 20:31:56 +00:00
MerryMage
b277bf5061
Correct FPSR and FPCR
2018-02-20 20:31:17 +00:00
MerryMage
7673933a9b
A64: Implement USHL
2018-02-20 19:48:15 +00:00
MerryMage
8d0e558271
A64: Implement UCVTF (vector, integer), scalar variant
2018-02-20 19:11:35 +00:00
MerryMage
da9a4f8877
A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point)
2018-02-20 18:45:28 +00:00
MerryMage
747968416f
A64: Implement system register TPIDR_EL0
2018-02-20 17:56:20 +00:00
MerryMage
0fd75fd9cb
A64: Implement system registers FPCR and FPSR
2018-02-20 17:38:29 +00:00
MerryMage
31e370cdf4
A64: Implement system register CNTPCT_EL0
2018-02-20 16:56:05 +00:00
MerryMage
9a88fd3340
A64: Implement system register CTR_EL0
2018-02-20 16:44:13 +00:00
MerryMage
1d16896d25
A64: Implement NEG (vector)
2018-02-20 15:41:07 +00:00
MerryMage
3184edf4a9
IR: Add IR instruction ZeroVector
2018-02-20 15:41:07 +00:00
MerryMage
31f8fbc5b8
emit_x64_floating_point: Add maybe_unused to preprocess parameter
2018-02-20 15:41:07 +00:00
MerryMage
567eb1a2f1
A64: Implement FMINNM (scalar)
2018-02-20 14:14:40 +00:00
MerryMage
c6d8fa1d36
A64: Implement FMAXNM (scalar)
2018-02-20 14:05:14 +00:00
MerryMage
616056d9a3
constant_pool: Add frame parameter
2018-02-20 14:04:48 +00:00
MerryMage
a3747cb01c
A64: Implement ADDP (scalar)
2018-02-18 23:55:38 +00:00
MerryMage
5cd5d9f5f8
reg_alloc: Only exchange GPRs
2018-02-18 23:24:15 +00:00
MerryMage
dd0452a435
A64: Implement DUP (element), scalar variant
2018-02-18 18:58:01 +00:00
MerryMage
e5732ea66f
emit_x64_floating_point: Correct FP{Max,Min}{32,64} implementations for -0/+0
2018-02-18 15:19:10 +00:00
MerryMage
40eb9c3253
A64: Implement FMAX (scalar), FMIN (scalar)
2018-02-18 13:49:23 +00:00
MerryMage
7cef39bdb4
fuzz_with_unicorn: QEMU's implementation of FCVT is incorrect
2018-02-18 13:47:41 +00:00
MerryMage
826dce212e
travis: Switch unicorn repository
2018-02-18 13:21:29 +00:00
MerryMage
9605f28792
a64/config: Allow NaN emulation accuracy to be set
2018-02-18 13:18:22 +00:00
MerryMage
e9435bc191
a64_emit_x64: Add conf to A64EmitContext
2018-02-18 13:18:22 +00:00
MerryMage
30b596df19
fuzz_with_unicorn: Explicitly test floating point instructions
2018-02-18 13:18:22 +00:00
MerryMage
be292a819c
A64: Implement FSQRT (scalar)
2018-02-18 13:18:22 +00:00
MerryMage
3c42d48a3f
backend_x64: Accurately handle NaNs
2018-02-18 13:18:22 +00:00
MerryMage
4aefed05d5
fuzz_with_unicorn: Print AArch64 disassembly
2018-02-18 13:18:22 +00:00
MerryMage
e585e1d49e
T32: Add initial decoder list
2018-02-14 19:29:19 +00:00
MerryMage
1598af4f12
simd_three_same: Add VectorZeroUpper to CMGE (vector) and CMHS (vector)
2018-02-13 19:01:47 +00:00
MerryMage
029ae11040
A64: Implement CMGT (zero), CMEQ (zero), CMLT (zero)
2018-02-13 19:01:21 +00:00
MerryMage
91483ab975
decoder/a64: Rearrange SIMD two-register misc decoders
2018-02-13 18:51:43 +00:00
MerryMage
9158534048
A64: Implement CMGE (register)
2018-02-13 18:29:54 +00:00
MerryMage
41e421bf0b
A64: Implement CMHI, CMHS
2018-02-13 18:20:18 +00:00
MerryMage
324810cfad
IR: Implement Vector{Less,Greater}{,Equal}{Signed,Unsigned}
2018-02-13 18:20:00 +00:00
