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Author SHA1 Message Date
Lioncash
72eb6ad362 ir: Add opcodes for signed saturated doubling multiplies 2018-09-06 20:35:43 +01:00
Lioncash
0f8ae84c80 externals: Update catch to 2.4.0 
Keeps the unit testing library up to date.
 2018-09-06 20:33:10 +01:00
Lioncash
235165ba70 A64: Implement SQABS' scalar variant 2018-09-06 15:49:25 +01:00
Lioncash
1adca93d4a A64: Implement SQABS' vector variant. 2018-09-06 15:49:25 +01:00
Lioncash
f978c445fa ir: Add opcodes for signed saturated absolute values 2018-09-06 15:49:25 +01:00
MerryMage
d895a84e72 emit_x64_floating_point: EmitFPToFixed: maxsd optimization 
maxsd is not required when doing a signed conversion, because x64
produces a 0x80...00 value for out of range values.
 2018-09-06 15:44:09 +01:00
MerryMage
c624fe3ff3 emit_x64_floating_point: ZeroIfNaN: pxor -> xorps 
xorps is shorter and more appropriate here.
 2018-09-05 22:00:36 +01:00
MerryMage
e987a84062 IR: Simplify FP{Single,Double}ToFixed{U,S}{32,64} 2018-09-05 21:04:40 +01:00
Lioncash
f1babc8924 externals: Update catch to 2.3.0 
Keeps the unit-testing library up to date.
 2018-09-03 17:56:02 +01:00
Lioncash
a0c587ac1a A32/decoder: Add missing <algorithm> includes 
These includes should be present, as we use std::find_if() within these headers.
 2018-09-03 13:53:26 +01:00
Lioncash
0435ac2d80 emit_x64_vector: Provide AVX path for EmitVectorMinU64() 2018-08-31 21:15:48 +01:00
Lioncash
5e40b8fcf8 emit_x64_vector: Provide AVX path for EmitVectorMinS64() 2018-08-31 21:15:48 +01:00
Lioncash
26bc231b47 emit_x64_vector: Provide AVX path for EmitVectorMaxU64() 2018-08-31 21:15:48 +01:00
Lioncash
ae734a7a8e emit_x64_vector: Provide AVX path for EmitVectorMaxS64() 2018-08-31 21:15:48 +01:00
Lioncash
1d0334c8cb emit_x64_vector: Simplify EmitVectorLogicalLeftShift8() 
Similar to EmitVectorLogicalRightShift8(), we can determine a mask ahead
of time and just and the results of a halfword left shift.
 2018-08-31 19:44:54 +01:00
Lioncash
f4a1196e60 emit_x64_vector: Simplify EmitVectorLogicalShiftRight8() 
We can generate the mask and AND it against the result of a halfword
shift instead of looping.
 2018-08-31 19:44:54 +01:00
Lioncash
4fc51f41b1 emit_x64_vector: Amend value definition in SSE 4.1 path for EmitVectorSignExtend16() 
We should be defining the value after the results have been calculated
to be consistent with the rest of the code.
 2018-08-31 13:48:32 +01:00
Lioncash
e50adae441 emit_x64_vector: Remove fallback in EmitVectorSignExtend64() 
This is fairly trivial to do manually.
 2018-08-31 13:48:14 +01:00
Lioncash
0a364f385d emit_x64_vector: Remove fallback for EmitVectorSignExtend32() 
We can just do the extension manually, which gets rid of the need to
fall back here.
 2018-08-31 13:48:14 +01:00
Lioncash
799e519707 ir_emitter: Rename fpscr_controlled parameters to fpcr_controlled 
Part of addressing #333
 2018-08-28 18:43:01 +01:00
MerryMage
68ca03e8d4 a32/exception_generating: BPKT: Define unpredictable behaviour 
Define unpredictable behaviour to be BKPT executes conditionally
 2018-08-26 00:48:29 +01:00
MerryMage
42c0589881 A32: Add define_unpredictable_behaviour option 2018-08-26 00:48:27 +01:00
MerryMage
3262736fb6 A32/location_descriptor: Change formatting to use hex 2018-08-26 00:33:44 +01:00
MerryMage
f3bb54e042 microinstruction: A32ExceptionRaised causes CPU exception 2018-08-26 00:33:43 +01:00
MerryMage
2b4224bcb4 A32/types: CondToString: Add nv 2018-08-25 23:02:58 +01:00
MerryMage
0d17b076bd block_of_code: Hide NX support behind compiler flag 
Systems that require W^X can use the DYNARMIC_ENABLE_NO_EXECUTE_SUPPORT cmake option.
 2018-08-23 20:56:05 +01:00
MerryMage
1ee3f3d9e6 Implement perfmap 2018-08-23 15:09:19 +01:00
MerryMage
72ed55f143 a32_emit_x64: Fix incorrect BMI2 implementation for SetCpsr 
* The MSB for each byte in cpsr_ge were not being appropriately set.
* We also expand test coverage to test this case.
* We fix the disassembly of the MSR (imm) and MSR (reg) instructions as well.
 2018-08-23 14:48:23 +01:00
MerryMage
2a705d0393 backend/x64: Support W^X systems 
Closes #176.
 2018-08-22 13:21:23 +01:00
BreadFish64
c95f023403 Backend: Create "backend" folder 
similar to the "frontend" folder
 2018-08-22 13:13:46 +01:00
MerryMage
deb1ab62d4 A64/translate: Standardize arguments of helper functions 
Don't pass in IREmitter when TranslatorVisitor is already available.
 2018-08-21 12:26:46 +01:00
MerryMage
30b6a5ffca A64/translate: Standardize TranslatorVisitor abbreviation 
Prefer v to tv.
 2018-08-21 12:16:32 +01:00
MerryMage
f9cd96bb1a emit_x64_vector: Avoid recalculating addresses in EmitVectorTableLookup 2018-08-21 12:16:32 +01:00
Lioncash
a42f301c28 A64: Implement SQXTN, SQXTUN, and UQXTN's scalar variants 
We can implement these in terms of the vector variants
 2018-08-20 08:08:57 +01:00
Lioncash
8a822def14 A64: Implement SDOT and UDOT's (by element) variants 
Gets all of the dot product instructions out of the way.
 2018-08-20 08:06:59 +01:00
MerryMage
b604f0d237 emit_x64_vector: Don't load zero constant from memory in EmitVectorTableLookup 2018-08-19 21:33:33 +01:00
MerryMage
8ac462fca9 emit_x64_vector: Special-case is_defaults_zero && table_size == 2 in EmitVectorTableLookup 2018-08-19 21:32:54 +01:00
MerryMage
08fae72a57 emit_x64_vector: Release registers when possible in EmitVectorTableLookup 2018-08-19 21:08:00 +01:00
MerryMage
c7d264bbe2 reg_alloc: Add the ability to Release an allocation early 2018-08-19 21:07:37 +01:00
MerryMage
3172a4b066 emit_x64_vector: Special-case table_size == 1 in EmitVectorTableLookup 2018-08-19 09:29:41 +01:00
MerryMage
50c589b2b5 emit_x64_vector: SSE4.1 implementation of EmitVectorTableLookup 2018-08-18 22:07:58 +01:00
MerryMage
bc6cf3021f A64: Implement TBL and TBX 2018-08-18 22:00:03 +01:00
MerryMage
8067ab9553 IR: Add VectorTable and VectorTableLookup IR instructions 2018-08-18 21:59:44 +01:00
MerryMage
0e0e839ba0 opcodes: Cleanup opcodes table 
* Remove T:: prefix from types.
* Add another column for a 4th argument.
 2018-08-18 19:39:59 +01:00
Lioncash
8e47d44c4d A64: Implement SDOT and UDOT's vector variant 2018-08-18 15:19:39 +01:00
Lioncash
3a367f341f A64: Implement SADALP and UADALP 
While we're at it we can join the code for SADDLP and UADDLP with these
instructions, since the only difference is we do an accumulate at the
end of the operation.
 2018-08-18 14:24:43 +01:00
Lioncash
5f322a160f A64: Implement SRSHL and URSHL 
Implements both scalar and vector variants.
 2018-08-18 14:23:29 +01:00
Lioncash
a278775c43 ir: Add opcodes for performing rounding left shifts 2018-08-18 14:23:29 +01:00
MerryMage
720efe337e emit_x64_floating_point: Fix smallest normal check in EmitFPMulAdd 2018-08-18 13:49:19 +01:00
Lioncash
fc96d512c9 A64: Implement ISB 
Given we want to ensure that all instructions are fetched again, we can
treat an ISB instruction as a code cache flush.
 2018-08-18 13:30:54 +01:00