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1356 Commits

Author SHA1 Message Date
Lioncash
9923ea0b71 A64: Implement SUQADD's scalar and vector variants 2018-09-09 17:06:03 +01:00
Lioncash
4c0adbb7f1 ir: Add opcodes for signed saturated accumulations of unsigned values 2018-09-09 17:06:03 +01:00
Lioncash
799bfed2df A64: Implement SMLAL{2}, SMLSL{2}, UMLAL{2}, and UMLSL{2}'s vector by-element variants 
We can simply modify the general function made for SMULL{2} and
UMULL{2}'s by-element variants to also handle the other multiply-based
by-element variants.
 2018-09-09 13:55:40 +01:00
Lioncash
94451ec321 A64: Implement UMULL{2}'s vector by-element variant 2018-09-09 13:55:40 +01:00
Lioncash
45867deac9 A64: Implement SMULL{2}'s vector by-element variant 2018-09-09 13:55:40 +01:00
Lioncash
02357939ac ir/value: Replace includes with forward declarations 
enum classes are still considered complete types when forward declared
(as the compiler knows the exact size of the type from the declaration
alone). The only difference in this case being that the members of the
enum class aren't visible. Given we don't use the members within this
header in any way, we can simply forward declare them here and remove
the inclusions.
 2018-09-09 09:04:22 +01:00
Lioncash
450f721df5 ir/cond: Migrate to C++17 nested namespace specifiers 2018-09-09 09:03:42 +01:00
Lioncash
e649988cd6 CMakeLists: Add missing cond.h header to file listing 
Allows the file to show up within IDEs more easily.
 2018-09-09 09:03:42 +01:00
Lioncash
d20e7694dd A64: Implement URSQRTE 2018-09-09 00:37:28 +01:00
Lioncash
4f3bde5f12 ir: Add opcodes for performing unsigned reciprocal square root estimates 2018-09-09 00:37:28 +01:00
Lioncash
cfeeaec1c6 A64: Implement URECPE 2018-09-09 00:37:28 +01:00
Lioncash
622b60efd6 ir: Add opcodes for unsigned reciprocal estimate 2018-09-09 00:37:28 +01:00
Lioncash
b575b23ea9 A64: Implement SQNEG's scalar and vector variant 2018-09-08 11:23:32 +01:00
Lioncash
06062a91c5 A64: Add opcodes for signed saturating negations 2018-09-08 11:23:32 +01:00
Lioncash
1c40579de5 emit_x64_vector: Simplify "position == 0" case for EmitVectorExtract() 
In the event position is zero, we can just treat it as a NOP, given
there's no need to move the data.
 2018-09-08 11:23:32 +01:00
Lioncash
e335050886 emit_x64_vector: Simplify "position == 0" case for EmitVectorExtractLower() 
In the event position == 0, we can just treat it as a simple movq,
clearing the upper half of the XMM register. This also makes that case
use only one register.
 2018-09-08 11:23:32 +01:00
Lioncash
8b13421bac A64: Implement SQDMULH's by-element scalar variant 2018-09-08 11:23:32 +01:00
Lioncash
9122a6e19e A64: Implement SQDMULH's by-element vector variant 2018-09-08 11:23:32 +01:00
MerryMage
176e60ebb1 backend/x64: Do not clear fast_dispatch_table if not enabled 
There is no need to pay for the cost of setting a large block of memory if we're not using it.
 2018-09-08 11:23:32 +01:00
MerryMage
959446573f A64: Implement FastDispatchHint 2018-09-07 22:07:44 +01:00
MerryMage
2be95f2b3b A32: Implement FastDispatchHint 2018-09-07 22:07:44 +01:00
MerryMage
96f23acd00 ir/terminal: Add FastDispatchHint 2018-09-07 21:29:47 +01:00
Lioncash
f5ca9e9e4a A64: Implement SQDMULH's scalar variant 2018-09-06 20:35:43 +01:00
Lioncash
af8bea59d5 ir: Add opcodes for scalar signed saturated doubling multiplies 2018-09-06 20:35:43 +01:00
Lioncash
fed4220dc0 A64: Implement SQDMULH's vector variant 2018-09-06 20:35:43 +01:00
Lioncash
72eb6ad362 ir: Add opcodes for signed saturated doubling multiplies 2018-09-06 20:35:43 +01:00
Lioncash
235165ba70 A64: Implement SQABS' scalar variant 2018-09-06 15:49:25 +01:00
Lioncash
1adca93d4a A64: Implement SQABS' vector variant. 2018-09-06 15:49:25 +01:00
Lioncash
f978c445fa ir: Add opcodes for signed saturated absolute values 2018-09-06 15:49:25 +01:00
MerryMage
d895a84e72 emit_x64_floating_point: EmitFPToFixed: maxsd optimization 
maxsd is not required when doing a signed conversion, because x64
produces a 0x80...00 value for out of range values.
 2018-09-06 15:44:09 +01:00
MerryMage
c624fe3ff3 emit_x64_floating_point: ZeroIfNaN: pxor -> xorps 
xorps is shorter and more appropriate here.
 2018-09-05 22:00:36 +01:00
MerryMage
e987a84062 IR: Simplify FP{Single,Double}ToFixed{U,S}{32,64} 2018-09-05 21:04:40 +01:00
Lioncash
a0c587ac1a A32/decoder: Add missing <algorithm> includes 
These includes should be present, as we use std::find_if() within these headers.
 2018-09-03 13:53:26 +01:00
Lioncash
0435ac2d80 emit_x64_vector: Provide AVX path for EmitVectorMinU64() 2018-08-31 21:15:48 +01:00
Lioncash
5e40b8fcf8 emit_x64_vector: Provide AVX path for EmitVectorMinS64() 2018-08-31 21:15:48 +01:00
Lioncash
26bc231b47 emit_x64_vector: Provide AVX path for EmitVectorMaxU64() 2018-08-31 21:15:48 +01:00
Lioncash
ae734a7a8e emit_x64_vector: Provide AVX path for EmitVectorMaxS64() 2018-08-31 21:15:48 +01:00
Lioncash
1d0334c8cb emit_x64_vector: Simplify EmitVectorLogicalLeftShift8() 
Similar to EmitVectorLogicalRightShift8(), we can determine a mask ahead
of time and just and the results of a halfword left shift.
 2018-08-31 19:44:54 +01:00
Lioncash
f4a1196e60 emit_x64_vector: Simplify EmitVectorLogicalShiftRight8() 
We can generate the mask and AND it against the result of a halfword
shift instead of looping.
 2018-08-31 19:44:54 +01:00
Lioncash
4fc51f41b1 emit_x64_vector: Amend value definition in SSE 4.1 path for EmitVectorSignExtend16() 
We should be defining the value after the results have been calculated
to be consistent with the rest of the code.
 2018-08-31 13:48:32 +01:00
Lioncash
e50adae441 emit_x64_vector: Remove fallback in EmitVectorSignExtend64() 
This is fairly trivial to do manually.
 2018-08-31 13:48:14 +01:00
Lioncash
0a364f385d emit_x64_vector: Remove fallback for EmitVectorSignExtend32() 
We can just do the extension manually, which gets rid of the need to
fall back here.
 2018-08-31 13:48:14 +01:00
Lioncash
799e519707 ir_emitter: Rename fpscr_controlled parameters to fpcr_controlled 
Part of addressing #333
 2018-08-28 18:43:01 +01:00
MerryMage
68ca03e8d4 a32/exception_generating: BPKT: Define unpredictable behaviour 
Define unpredictable behaviour to be BKPT executes conditionally
 2018-08-26 00:48:29 +01:00
MerryMage
42c0589881 A32: Add define_unpredictable_behaviour option 2018-08-26 00:48:27 +01:00
MerryMage
3262736fb6 A32/location_descriptor: Change formatting to use hex 2018-08-26 00:33:44 +01:00
MerryMage
f3bb54e042 microinstruction: A32ExceptionRaised causes CPU exception 2018-08-26 00:33:43 +01:00
MerryMage
2b4224bcb4 A32/types: CondToString: Add nv 2018-08-25 23:02:58 +01:00
MerryMage
0d17b076bd block_of_code: Hide NX support behind compiler flag 
Systems that require W^X can use the DYNARMIC_ENABLE_NO_EXECUTE_SUPPORT cmake option.
 2018-08-23 20:56:05 +01:00
MerryMage
1ee3f3d9e6 Implement perfmap 2018-08-23 15:09:19 +01:00