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Author	SHA1	Message	Date
MerryMage	a1f642f838	emit_x64_floating_point: F16C implementation of FPSingleToHalf	2019-03-24 15:42:14 +00:00
MerryMage	2a5b4f4933	emit_x64_floating_point: F16C implementation of FPHalfToSingle and FPHalfToDouble	2019-03-24 11:42:22 +00:00
MerryMage	59887e8b62	emit_x64_floating_point: Factor out ConvertRoundingModeToX64Immediate	2019-03-24 11:28:04 +00:00
MerryMage	16a40b3b9d	backend/x64: Expose FPCR in EmitContext instead of its subcomponents	2019-03-24 11:28:04 +00:00
Merry	d5263c17cb	Merge pull request #458 from lioncash/float-op ... A64: Handle half-precision floating point in FABS, FNEG, and scalar FMOV	2019-03-24 11:23:21 +00:00
Merry	42ae48e768	Merge pull request #457 from lioncash/fpconv ... A64: Handle half-precision floating point in floating-point FCVT, FCVTL, and FCVTN	2019-03-23 20:59:20 +00:00
Lioncash	f12b0f926c	A64: Handle half-precision floating point in FCVTL ... Like FCVTN, now that we have half-precision floating point conversion functions available, we can go ahead and use those to eliminate the interpreter fallback.	2019-03-23 14:16:44 -04:00
Lioncash	d4d642198c	A64: Handle half-precision floating point in FCVTN ... Now that we have IR instructions for performing conversions with half-precision floating point, we can also handle half-precision values within FCVTN.	2019-03-23 14:16:44 -04:00
Lioncash	ede3d7284a	A64: Enable FCVT floating-point conversions for half-precision ... With this, we no longer have to fall back to the interpreter in any of the FCVT floating-point conversion instructions.	2019-03-23 14:16:44 -04:00
Lioncash	eb09ae27db	frontend/ir_emitter: Add half->{single, double} and {double, single}->half conversion opcodes	2019-03-23 14:16:44 -04:00
Lioncash	f74c9dad6f	common/fp/unpacked: Amend behavior of FPUnpackCV ... This is supposed to call FPUnpackBase instead of FPUnpack. This would result in alternate half-precision representations being misinterpreted when it comes to dealing with NaNs.	2019-03-23 14:16:44 -04:00
Lioncash	36e739ba9b	common/fp/op/FPConvert: Amend off-by one in double NaN case in FPConvertNaN ... Avoids potentially clobbering the intended sign bit value during conversions to double-precision values. The other conversion types are already properly handled, so those don't need to be addressed.	2019-03-23 14:16:44 -04:00
Lioncash	29e1a024c7	common/fp/op/FPConvert: Add half-precision instantiations to FPConvert	2019-03-23 14:16:37 -04:00
Lioncash	d59cff531c	A64: Handle half-precision floating point in scalar FMOV ... This is simply performing a scalar value transfer between registers without conversions, so this is trivial to handle as-is.	2019-03-23 13:46:47 -04:00
Lioncash	5196e94792	A64: Handle half-precision floating point in scalar FABS ... Now that we have the half-precision variant of the opcode added, we can simply handle the instruction instead of treating it as undefined.	2019-03-23 13:39:23 -04:00
Lioncash	c75f73785d	frontend/ir_emitter: Add half-precision variant of FPAbs	2019-03-23 13:38:09 -04:00
Lioncash	b772cb7c5a	A64: Handle half-precision floating point in scalar FNEG ... With the half-precision variant of the FPNeg opcode added, we can utilize it here to emulate the half-precision variant of FNEG.	2019-03-23 13:23:34 -04:00
Lioncash	fd71df5efd	frontend/ir_emitter: Add half-precision variant of FPNeg	2019-03-23 13:21:59 -04:00
Merry	0f2f6ef789	Merge pull request #456 from lioncash/mov ... A64: Enable FMOV (general) for half-precision floating point	2019-03-22 22:27:48 +00:00
Lioncash	7627fa389b	A64: Enable FMOV (general) for half-precision floating point ... This just transfers values between vector registers and general-purpose registers with no conversions performed, so this is trivial to add support for half-precision to.	2019-03-22 15:18:12 -04:00
Merry	004adfe844	Merge pull request #455 from lioncash/sqrdmulh-scalar ... A64: Implement SQRDMULH and SQDMULL's scalar indexed variants	2019-03-22 12:43:53 +00:00
Merry	a3a41a91cd	Merge pull request #454 from lioncash/sqrdmulh ... A64: Implement SQRDMULH and SQDMULL{2}'s vector indexed element variants	2019-03-21 19:14:30 +00:00
Lioncash	5c6becc402	A64: Implement SQRDMULH's scalar indexed element variant	2019-03-20 23:26:55 -04:00
Lioncash	2d78390d43	A64: Implement SQDMULL{2}'s scalar indexed element variant	2019-03-20 23:05:07 -04:00
Lioncash	3238864878	simd_scalar_x_indexed_element: Factor out index and Vm argument construction ... This will be useful in the implementations of SQRDMULH and SQDMULL{2} as well.	2019-03-20 22:28:46 -04:00
Lioncash	996a618643	simd_vector_x_indexed_element: Deduplicate index and Vm operand construction	2019-03-20 16:21:48 -04:00
Lioncash	328211b0c5	A64: Implement SQDMULL{2}'s by-element variant	2019-03-20 15:36:27 -04:00
Lioncash	b4ca6b67d1	A64: Implement SQRDMULH's by-index vector variant	2019-03-20 14:05:41 -04:00
Merry	6e8b7d27ec	Merge pull request #452 from lioncash/frecpx ... A64: Implement FRECPX's half-precision floating-point variant	2019-03-10 20:43:55 +00:00
Lioncash	f8ad1819ab	A64: Implement FRECPX's half-precision floating point variant	2019-03-09 20:08:01 -05:00
Lioncash	db67a42244	frontend/ir/ir_emitter: Amend FPRecipExponent to handle half-precision floating point	2019-03-09 20:08:01 -05:00
Lioncash	8036a54a74	frontend/ir/value: Add U16U32U64 type to represent floating point types	2019-03-09 20:08:01 -05:00
Lioncash	1e0933907a	common/fp/op/FPRecipExponent: Add half-precision floating point specialization	2019-03-09 20:07:53 -05:00
Lioncash	5117997cde	common/fp/unpacked: Correct edge-cases within FPUnpack for half-precision floating point ... This corrects one case where floating-point exceptions could be set when they're not supposed to be. This also corrects a case where values were being treated as NaNs when they weren't supposed to be.	2019-03-09 19:21:16 -05:00
Merry	d3e242b4af	Merge pull request #451 from lioncash/unpck ... common/fp: Minor adjustments for half-precision floating point support	2019-03-09 16:05:42 +00:00
Lioncash	1b66e43094	common/fp/process_nan: Add half-precision instantiations for NaN processing functions	2019-03-09 02:26:58 -05:00
Lioncash	2f7f75ff09	common/fp/unpacked: Add half-precision instantiation of FPRoundBase	2019-03-09 02:26:47 -05:00
Lioncash	74e230de9d	common/fp/unpacked: Handle half-precision unpacking in FPUnpackBase	2019-03-09 01:19:55 -05:00
Lioncash	9c96c4c9fc	common/fp/unpacked: Adjust FPUnpack to operate like ARM pseudocode ... This function is defined as always disabling the AHP bit in the fpcr before performing any operations. At the same time, rename the original FPUnpack function to FPUnpackBase to match the pseudocode in the ARM reference manual.	2019-03-09 00:08:12 -05:00
Merry	c535f4bf89	Merge pull request #448 from lioncash/saturate ... A64: Implement SQSHRN, SQSHRUN, and UQSHRN's scalar variants	2019-03-08 18:50:18 +00:00
Merry	b3d6f40dbb	Merge pull request #449 from lioncash/hp ... common/fp/info: Add specialization of FPInfo for half-precision floating point	2019-03-08 18:49:18 +00:00
Merry	d2fbcc6dde	Merge pull request #450 from lioncash/cv ... common/fp/unpacked: Add FPRoundCV and FPUnpackCV	2019-03-08 12:05:52 +00:00
Lioncash	6dad779547	common/fp/unpacked: Add FPRoundCV ... Corresponds to the equivalent pseudocode within the ARMv8 reference manual. This will be necessary for supporting half-precision floating-point. This also makes use of it within FPConvert	2019-03-08 06:24:54 -05:00
Lioncash	deca5e5dae	common/fp/unpacked: Add FPUnpackCV ... Adds a template function that performs the same behavior as in the ARM pseudocode, and utilizes it in FPConvert, which will be necessary for half-float support.	2019-03-08 06:20:54 -05:00
Lioncash	d1a1434af6	common/fp/info: Add specialization of FPInfo for half-precision floating point ... Puts the necessary info struct in place for further use.	2019-03-08 03:50:48 -05:00
Lioncash	203678bd9e	A64: Implement SQSHRN, SQSHRUN, and UQSHRN's scalar variants ... These can just be implemented in terms of the vector variants for the time being.	2019-03-08 03:23:56 -05:00
Lioncash	fb3847b044	A64: Amend prototypes of some SIMD scalar shift by immediate opcodes ... These take a vector for a destination.	2019-03-08 00:20:24 -05:00
Merry	40339b1278	Merge pull request #447 from lioncash/flag ... A64: Implement CFINV, RMIF, AXFlag and XAFlag	2019-03-07 16:17:13 +00:00
Lioncash	8d115ae80d	ir_opt/a64_get_set_elimination_pass: Add handling for NZCV raw get and set operations	2019-03-07 03:57:18 -05:00
Lioncash	5b66ae2a5a	A64: Implement AXFlag and XAFlag	2019-03-06 18:39:19 -05:00