Citra-emu/dynarmic
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
775 Commits 9 Branches 0 Tags
Commit Graph

775 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
MerryMage
ef6b4f20ca a64_emit_x64: Use xword from Xbyak::util 2018-01-26 18:38:30 +00:00
Lioncash
8c013e7928 General: Convert multiple namespace specifiers to nested namespace specifiers where applicable 
Makes namespacing a little less noisy
 2018-01-26 17:06:48 +00:00
Lioncash
792cb91753 A64: Zero upper 64 bits in ORN if using the 64-bit variant 
Resolves a TODO
 2018-01-26 17:06:26 +00:00
Lioncash
07930f0253 unicorn: Display EC and ISS separately beside the full ESR value 
Makes it a little nicer to pick out the exception class details at a glance
 2018-01-26 12:31:43 +00:00
Lioncash
e99cbcf4e3 unicorn: Use static_cast instead of reinterpret_cast 
It's well-defined to cast from void* back to the original pointer type.
 2018-01-26 12:31:33 +00:00
MerryMage
a3af4dd218 load_store_register_unprivileged: bug: LDTRSW 2018-01-26 02:03:16 +00:00
MerryMage
06bea0ceaa A64: Implement CMEQ (register, vector) 2018-01-26 01:52:42 +00:00
MerryMage
f7e8a2259a IR: Implement IR instructions VectorEqual{8,16,32,64,128} 2018-01-26 01:52:06 +00:00
MerryMage
f833a17906 reg_alloc: Use std::exchange 2018-01-26 01:51:04 +00:00
Fernando Sahmkow
5ffd11d140 A64: Implemented EOR (vector), ORR (vector, register) and ORN (vector) Instructions (#142) 2018-01-26 00:57:56 +00:00
Lioncash
fc82109071 unicorn_load: Minor Windows-related changes 
- Add missing include
- Fix a potential compilation issue where the constructor wouldn't be able to execute, as it would be private.
 2018-01-26 00:52:46 +00:00
MerryMage
d08b738662 tests/A64: Test memory writes 2018-01-25 23:56:57 +00:00
MerryMage
d99c99aabb microinstruction: Missed A64{Read,Write}Memory128 from opcode information 2018-01-25 23:56:14 +00:00
MerryMage
85034beaac emit_x64_packed: EmitPackedSubU16 modified xmm_b wasn't writeable 
For CPUs that didn't support SSE4.1, this was a bug.
 2018-01-25 18:41:53 +00:00
Lioncash
1ffe4e03d9 tests: Fix truncation in GetFpcr() 2018-01-25 18:26:32 +00:00
James Rowe
0cc1bce1a8 Fixup: Xn|SP are 64 bit addresses encoded in the Rn field 2018-01-25 17:46:14 +00:00
James Rowe
76aaa84687 A64: Fix bugs and address review comments 2018-01-25 17:46:14 +00:00
James Rowe
7825ae3a4f Add missing returns 2018-01-25 17:46:14 +00:00
James Rowe
ddb5b3469d A64: Implement Load/Store register (unprivileged) 2018-01-25 17:46:14 +00:00
MerryMage
7f3a790de5 fixup: travis: Test with disabled CPU feature detection 2018-01-24 19:42:54 +00:00
Lioncash
850337e434 CMakeLists: Add opcodes.inc to the source file list 
Allows the file to show up nicely within IDEs
 2018-01-24 19:42:02 +00:00
MerryMage
7d389fb5f8 travis: Test with disabled CPU feature detection 
Ensure that fallbacks are working correctly.
 2018-01-24 19:22:45 +00:00
MerryMage
314e020992 IR: Add IR instruction VectorZeroUpper 2018-01-24 17:11:13 +00:00
MerryMage
8ce3e0518a a64_emit_x64: bug: EmitA64WriteMemory128 should write not read 2018-01-24 17:10:44 +00:00
FernandoS27
d1664096f5 Implemented SDIV and UDIV instructions 2018-01-24 17:09:00 +00:00
MerryMage
8873d17db2 A64: Implement LDR/STR (immediate, SIMD&FP) 2018-01-24 16:28:18 +00:00
MerryMage
7f5ce36368 IR: Add IR instructions A64Memory{Read,Write}128 
Add the Windows ABI implementation
 2018-01-24 16:28:18 +00:00
MerryMage
d6589fe3ee IR: Add IR instructions A64Memory{Read,Write}128 
This implementation only works on macOS and Linux.
 2018-01-24 16:18:58 +00:00
MerryMage
5421c90216 IR: Add IR instruction VectorGetElement{8,16,32,64} 2018-01-24 16:18:58 +00:00
MerryMage
3932d6d695 IR: Add IR instruction ZeroExtendToQuad 2018-01-24 16:18:58 +00:00
MerryMage
264c446e54 block_of_code: Add ABI_RETURN2 2018-01-24 16:18:58 +00:00
MerryMage
ed63cc7ae9 interface: Move Vector typedef to config.h 2018-01-24 16:18:58 +00:00
MerryMage
ef81c2bcfc bit_util: bug: Infinite loop in HighestSetBit 2018-01-24 16:18:58 +00:00
MerryMage
1db423b2ad A64: Implement DUP (general) 2018-01-24 12:01:26 +00:00
MerryMage
6f1c44e311 IR: Implement Vector{Lower,}Broadcast{8,16,32,64} 2018-01-24 12:01:26 +00:00
Lioncash
cdb588dab5 General: Default constructors and destructors where applicable 2018-01-24 09:07:22 +00:00
Lioncash
e300f1de46 ir_emitter: Remove unused includes 2018-01-24 01:50:10 +00:00
Lioncash
0e5988258d A64: Implement RBIT 2018-01-24 01:49:58 +00:00
MerryMage
ae603909d6 ir_emitted: Remove unimplemented IR instruction Unimplemented 2018-01-23 22:16:15 +00:00
MerryMage
f014a5bec7 emit_x64: Extract BlockRangeInformation, remove template parameter 2018-01-23 19:44:35 +00:00
MerryMage
5f5e664a66 emit_x64: Use JitStateInfo 2018-01-23 19:44:35 +00:00
MerryMage
d52cb2d0de A64: Implement CLS 
This is not the cleanest implementation.
 2018-01-23 19:44:35 +00:00
MerryMage
24383e543b A64: Implement ADDP (vector) 2018-01-23 17:46:28 +00:00
MerryMage
dfcbe5bd2f IR: Implement Vector{Lower,}PairedAdd{8,16,32,64} 2018-01-23 17:46:28 +00:00
MerryMage
961e64dfaf backend_x64: Split emit_x64 2018-01-23 17:46:28 +00:00
MerryMage
41d9a6421d fuzz_with_unicorn: Compare vectors 2018-01-23 17:46:28 +00:00
MerryMage
2b59e2ba0b microinstruction: bug: Add missing opcodes 2018-01-23 17:46:28 +00:00
Lioncash
bd00d9bc80 A64: Implement SMADDL, SMSUBL, UMADDL, and UMSUBL 2018-01-23 16:08:05 +00:00
Lioncash
768e5bcf9c A64: Implement MADD and MSUB 2018-01-23 16:08:05 +00:00
Lioncash
ffaf837e58 A64: Implement CLZ 2018-01-23 11:55:09 +00:00