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Author SHA1 Message Date
Lioncash
f0ecc27f2f A64: Implement USRA (scalar) 2018-04-13 16:05:18 +01:00
Lioncash
1e71835cb1 A64: Implement USHR (scalar) 2018-04-13 16:05:18 +01:00
Lioncash
746969bbe6 A64: Implement SHL (scalar) 2018-04-13 16:05:18 +01:00
Lioncash
a90cddaa05 A64: Implement SM3PARTW1 2018-04-13 15:22:10 +01:00
Lioncash
7570ea1a33 simd_sha512: Simplify RAX1 
Now that the vector rotation helpers are in, replace the explicit
shifting with the relevant helper function that does the same thing.

Simply tidies up code; no behavioral changes are made.
 2018-04-13 06:31:09 +01:00
Lioncash
c7c2fa2b66 A64: Implement SM3PARTW2 2018-04-12 09:21:51 +01:00
Lioncash
987ca9566b ir: Add helper functions for vector rotation 2018-04-12 09:21:51 +01:00
Lioncash
066cf3e7a7 A64: Implement SM3TT2B 2018-04-10 22:22:56 +01:00
Lioncash
bb7c0ab1ba A64: Implement SM3TT2A 2018-04-10 22:22:56 +01:00
Lioncash
3f81c90013 A64: Implement SM3TT1B 2018-04-10 18:30:33 +01:00
Lioncash
3e7483e1db A64: Implement SM3TT1A 2018-04-10 16:56:17 +01:00
Lioncash
8e739a73dc simd_shift_by_immediate: Merge signed/unsigned helper functions 
Gets rid of a little more code duplication.
 2018-04-10 16:43:59 +01:00
Lioncash
5f8f4d106a A64: Implement SM3SS1 2018-04-08 11:02:54 +01:00
Lioncash
c9c6ae101e A64: Implement SRI (vector) 2018-04-08 11:01:08 +01:00
Lioncash
4b9bdb2270 A64: Implement SLI (vector) 2018-04-08 11:01:08 +01:00
Lioncash
4e8fd68308 A64: Implement SRSRA (vector) 2018-04-08 10:55:27 +01:00
Lioncash
b3834adc2e A64: Implement SRSHR (vector) 2018-04-08 10:55:27 +01:00
MerryMage
6febae5f8e imm: Add additional bit position checks to Imm::Bits 2018-04-08 10:42:23 +01:00
MerryMage
5bc164adb9 math_util: rvalue references for std::forward 2018-04-08 10:37:11 +01:00
Lioncash
3fdaf77c7a A64: Implement SSUBL/SSUBL2 2018-04-07 15:20:58 +01:00
Lioncash
c669f091e6 A64: Implement SADDL/SADDL2 2018-04-07 15:20:58 +01:00
Lioncash
c144cb39c9 A64: Implement USUBL/USUBL2 2018-04-07 15:20:58 +01:00
Lioncash
14bc8bce7f A64: Implement UADDL/UADDL2 2018-04-07 15:20:58 +01:00
Lioncash
a000cb6e36 simd_shift_by_immediate: Factor out common code in shift instructions 
Gets rid of partial duplication of the same code for instructions that only have a small behavior difference to them.

e.g. The only difference between SSHR and SSRA is that SSRA adds an accumulator before storing the result.
 2018-04-07 15:20:28 +01:00
Lioncash
436eddcfa1 A64: Implement URSRA (vector) 2018-04-04 14:17:43 +01:00
Lioncash
c72c8bff0d A64: Implement URSHR (vector) 2018-04-04 14:17:43 +01:00
Lioncash
4f705d840f A64: Implement RSHRN/RSHRN2 2018-04-04 11:43:02 +01:00
Lioncash
6e3e03a48b A64: Implement SHRN/SHRN2 2018-04-04 11:43:02 +01:00
Lioncash
523c0fd0e0 A64/translate: Amend I() to also handle u8 and u16 immediates 
This is necessary for instructions like SRSHR, and other related instructions.
 2018-04-04 11:43:02 +01:00
MerryMage
f0ba929fc3 fuzz_with_unicorn: Correct GenRandomInst 
UnallocatedEncoding is now handled in ShouldTestInst
 2018-04-04 11:15:56 +01:00
MerryMage
3c3767e073 A64: Implement FMOV (vector, immediate) and mark other SIMD modified immediate instructions as unallocated 2018-04-04 10:36:27 +01:00
MerryMage
92e416a9b8 A64: Implement ZIP2 2018-04-04 10:23:04 +01:00
MerryMage
9891fb3b2c travis: Enable DYNARMIC_USE_LLVM 
Provides disassembly, which is useful for debugging failing tests
on CI.
 2018-04-04 09:17:38 +01:00
MerryMage
6968880eb6 decoder/a64: Tweak ordering algorithm 
Ensuring only instruction families are sorted with each other in
the fashion previously devised does not admit a total ordering.
 2018-04-04 09:14:41 +01:00
MerryMage
3a5b6ba709 ir_emitter: Remove overloads 
Having overloads made explicit casting necesssary for these functions when
using types like UAny.
 2018-04-03 23:13:52 +01:00
Lioncash
61fd0d4fdb A64: Implement RBIT (vector) 2018-04-03 21:18:03 +01:00
Lioncash
f921005a70 ir: Add opcode for reversing bits in a vector 2018-04-03 21:18:03 +01:00
Lioncash
4fc8daa103 A64/translate: Amend instruction prototypes erroneously marked as taking Reg 
Makes the prototypes consistent
 2018-04-03 18:05:01 +01:00
Lioncash
b4e944cd51 A64: Implement RAX1 2018-04-03 14:28:41 +01:00
Lioncash
d56bed53e6 a64_get_set_elimination_pass: Make TrackingType enum an enum class 
Prevents placing single letter enum members into the surrounding scope.
 2018-04-03 07:49:33 +01:00
Lioncash
748f624fe8 A64: Implement ABS (vector) 2018-04-03 07:49:08 +01:00
Lioncash
032b09cbdf ir: Add opcodes for performing vector absolute values 2018-04-03 07:49:08 +01:00
Lioncash
8cb52b48e6 A64: Implement USUBW/USUBW2 2018-04-03 07:48:26 +01:00
Lioncash
958e30a87a A64: Implement SSUBW/SSUBW2 2018-04-03 07:48:03 +01:00
Lioncash
8b3ff327bb A64: Implement SADDW/SADDW2 2018-04-03 07:48:03 +01:00
MerryMage
cfbe7cfd83 A64: Implement EXT 2018-04-02 22:10:28 +01:00
MerryMage
14d3d72aac IR: Implement VectorExtract, VectorExtractLower IR instructions 2018-04-02 21:52:46 +01:00
MerryMage
9d471a6899 A64: Implement UADDW 2018-04-02 21:51:40 +01:00
MerryMage
c56b6d0981 A64: Implement FMUL (vector) 2018-04-02 21:02:57 +01:00
Lioncash
19068dea1f A64: Implement UABA 
Now that we have unsigned absolute difference capabilities, we can just use this to
append onto the result via a vector add.
 2018-04-02 19:08:20 +01:00