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Author SHA1 Message Date
Lioncash
b3834adc2e A64: Implement SRSHR (vector) 2018-04-08 10:55:27 +01:00
MerryMage
6febae5f8e imm: Add additional bit position checks to Imm::Bits 2018-04-08 10:42:23 +01:00
MerryMage
5bc164adb9 math_util: rvalue references for std::forward 2018-04-08 10:37:11 +01:00
Lioncash
3fdaf77c7a A64: Implement SSUBL/SSUBL2 2018-04-07 15:20:58 +01:00
Lioncash
c669f091e6 A64: Implement SADDL/SADDL2 2018-04-07 15:20:58 +01:00
Lioncash
c144cb39c9 A64: Implement USUBL/USUBL2 2018-04-07 15:20:58 +01:00
Lioncash
14bc8bce7f A64: Implement UADDL/UADDL2 2018-04-07 15:20:58 +01:00
Lioncash
a000cb6e36 simd_shift_by_immediate: Factor out common code in shift instructions 
Gets rid of partial duplication of the same code for instructions that only have a small behavior difference to them.

e.g. The only difference between SSHR and SSRA is that SSRA adds an accumulator before storing the result.
 2018-04-07 15:20:28 +01:00
Lioncash
436eddcfa1 A64: Implement URSRA (vector) 2018-04-04 14:17:43 +01:00
Lioncash
c72c8bff0d A64: Implement URSHR (vector) 2018-04-04 14:17:43 +01:00
Lioncash
4f705d840f A64: Implement RSHRN/RSHRN2 2018-04-04 11:43:02 +01:00
Lioncash
6e3e03a48b A64: Implement SHRN/SHRN2 2018-04-04 11:43:02 +01:00
Lioncash
523c0fd0e0 A64/translate: Amend I() to also handle u8 and u16 immediates 
This is necessary for instructions like SRSHR, and other related instructions.
 2018-04-04 11:43:02 +01:00
MerryMage
f0ba929fc3 fuzz_with_unicorn: Correct GenRandomInst 
UnallocatedEncoding is now handled in ShouldTestInst
 2018-04-04 11:15:56 +01:00
MerryMage
3c3767e073 A64: Implement FMOV (vector, immediate) and mark other SIMD modified immediate instructions as unallocated 2018-04-04 10:36:27 +01:00
MerryMage
92e416a9b8 A64: Implement ZIP2 2018-04-04 10:23:04 +01:00
MerryMage
9891fb3b2c travis: Enable DYNARMIC_USE_LLVM 
Provides disassembly, which is useful for debugging failing tests
on CI.
 2018-04-04 09:17:38 +01:00
MerryMage
6968880eb6 decoder/a64: Tweak ordering algorithm 
Ensuring only instruction families are sorted with each other in
the fashion previously devised does not admit a total ordering.
 2018-04-04 09:14:41 +01:00
MerryMage
3a5b6ba709 ir_emitter: Remove overloads 
Having overloads made explicit casting necesssary for these functions when
using types like UAny.
 2018-04-03 23:13:52 +01:00
Lioncash
61fd0d4fdb A64: Implement RBIT (vector) 2018-04-03 21:18:03 +01:00
Lioncash
f921005a70 ir: Add opcode for reversing bits in a vector 2018-04-03 21:18:03 +01:00
Lioncash
4fc8daa103 A64/translate: Amend instruction prototypes erroneously marked as taking Reg 
Makes the prototypes consistent
 2018-04-03 18:05:01 +01:00
Lioncash
b4e944cd51 A64: Implement RAX1 2018-04-03 14:28:41 +01:00
Lioncash
d56bed53e6 a64_get_set_elimination_pass: Make TrackingType enum an enum class 
Prevents placing single letter enum members into the surrounding scope.
 2018-04-03 07:49:33 +01:00
Lioncash
748f624fe8 A64: Implement ABS (vector) 2018-04-03 07:49:08 +01:00
Lioncash
032b09cbdf ir: Add opcodes for performing vector absolute values 2018-04-03 07:49:08 +01:00
Lioncash
8cb52b48e6 A64: Implement USUBW/USUBW2 2018-04-03 07:48:26 +01:00
Lioncash
958e30a87a A64: Implement SSUBW/SSUBW2 2018-04-03 07:48:03 +01:00
Lioncash
8b3ff327bb A64: Implement SADDW/SADDW2 2018-04-03 07:48:03 +01:00
MerryMage
cfbe7cfd83 A64: Implement EXT 2018-04-02 22:10:28 +01:00
MerryMage
14d3d72aac IR: Implement VectorExtract, VectorExtractLower IR instructions 2018-04-02 21:52:46 +01:00
MerryMage
9d471a6899 A64: Implement UADDW 2018-04-02 21:51:40 +01:00
MerryMage
c56b6d0981 A64: Implement FMUL (vector) 2018-04-02 21:02:57 +01:00
Lioncash
19068dea1f A64: Implement UABA 
Now that we have unsigned absolute difference capabilities, we can just use this to
append onto the result via a vector add.
 2018-04-02 19:08:20 +01:00
Lioncash
62d49b32c2 A64: Implement UABD 2018-04-02 19:08:20 +01:00
Lioncash
734447ef3d ir: Add opcodes for performing vector unsigned absolute differences 2018-04-02 19:08:20 +01:00
Lioncash
5baa22b26b ir_emitter: Make immediate member functions const qualified 
These don't modify class state
 2018-04-02 19:07:26 +01:00
Lioncash
1e8fe95cc4 IR: Add opcodes for interleaving upper-order bytes/halfwords/words/doublewords 
I should have added this when I introduced the functions for interleaving
low-order equivalents for consistency in the interface.
 2018-03-31 11:01:38 +01:00
Lioncash
3970a8856d A64: Implement SHA1H 
This is a fairly trivial instruction it's essentially:

result = ROL(data, 30);
 2018-03-31 10:59:49 +01:00
Lioncash
cad9d31b83 emit_x64_data_processing: Deduplicate some code in zero-extension functions 
EmitZeroExtendByteToLong() can be implemented in terms of EmitZeroExtendByteToWord() and
EmitZeroExtendHalfToLong() can be implemented in terms of EmitZeroExtendHalfToWord().
 2018-03-29 20:59:50 +01:00
Lioncash
a94f321f69 A64: NOP immediate variant of PRFM 
Makes behavior identical to the literal variant of PRFM. Given this is simply a hint instruction,
this is valid behavior. The upside is that we don't fall back to Unicorn unnecessarily whenever
the instruction is encountered.
 2018-03-29 20:59:43 +01:00
MerryMage
9cc12d80b9 abi: Missing includes' 2018-03-29 12:46:29 +01:00
MerryMage
ac35ad5838 emit_x64_floating_point: Near jump instead of short jump in FPMinNumberic{32,64} 2018-03-29 12:45:33 +01:00
Lioncash
6f03fddee5 A64: system: Use an enum class for MRS/MSR register encodings 
Reduces the need to manually write out the register bit encodings repeatedly.
 2018-03-29 12:44:37 +01:00
MerryMage
12a102046c emit_X64_floating_point: Near jmp to end instead of short jmp 
Jump destination can be further than what can be reached in a short
jump under some FPCR options.
 2018-03-27 08:21:21 +01:00
Lioncash
6278f83560 emit_x64_vector: Fix typo in VectorShuffleImpl 
This is supposed to be pshufd, not pshufw (which only allows a 64-bit operand)
 2018-03-23 19:51:09 +00:00
Lioncash
25a0204203 A64: Implement REV64 2018-03-23 17:34:59 +00:00
Lioncash
aa92e33194 bit_util: Do nothing in RotateRight if the rotation amount is zero 
Without this sanitizing it's possible to perform a shift with a shift
amount that's the same size as the type being shifted. This actually
occurs when decoding ORR variants.

We could get fancier here and make this branchless, but we don't
really use RotateRight in any performance intensive areas.
 2018-03-21 19:30:02 +00:00
Lioncash
e537985584 A64: Implement REV32 (vector) 2018-03-21 15:40:03 +00:00
Lioncash
f62a258945 ir: Add IR opcodes for emitting vector shuffles 
This uses the ARM terminology for sizes (Halfword -> 2 bytes, Word -> 4 bytes)
as opposed to the x86 terminology of (Word -> 2 bytes, Double word -> 4 bytes)
 2018-03-21 15:40:03 +00:00