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Author SHA1 Message Date
Lioncash
fb3847b044
A64: Amend prototypes of some SIMD scalar shift by immediate opcodes 
These take a vector for a destination.
 2019-03-08 00:20:24 -05:00
Merry
40339b1278
Merge pull request #447 from lioncash/flag 
A64: Implement CFINV, RMIF, AXFlag and XAFlag
 2019-03-07 16:17:13 +00:00
Lioncash
8d115ae80d
ir_opt/a64_get_set_elimination_pass: Add handling for NZCV raw get and set operations 2019-03-07 03:57:18 -05:00
Lioncash
5b66ae2a5a
A64: Implement AXFlag and XAFlag 2019-03-06 18:39:19 -05:00
Lioncash
080d163d39
A64: Implement RMIF 2019-03-06 18:39:19 -05:00
Lioncash
9cd84c5149
A64: Implement CFINV 2019-03-06 18:39:12 -05:00
Merry
04f09eb644
Merge pull request #442 from lioncash/fcvtxn 
A64: Implement scalar and vector variants of FCVTXN
 2019-03-06 20:27:59 +00:00
Lioncash
27af30d7c3
ir: Add A64-specific opcodes for getting and setting raw NZCV values 
This will be necessary to implement the flag manipulation and flag
format instructions.
 2019-03-06 14:17:27 -05:00
Lioncash
cdfdd95e63
A64: Implement the vector version of FCVTXN 2019-03-06 12:05:24 -05:00
Lioncash
e3ba07971e
A64: Implement the scalar version of FCVTXN 2019-03-06 12:05:24 -05:00
Lioncash
f44cafe3ca
frontend/ir/ir_emitter: Alter parameters of FPDoubleToSingle() and FPSingleToDouble() to pass along desired rounding mode 
This will be necessary to special-case the non-IEEE Von Neumann rounding
to odd rounding mode.
 2019-03-06 12:05:20 -05:00
Merry
d0ae8dcf97
Merge pull request #446 from lioncash/sqshl 
A64: Implement scalar variants of SQSHL (register) and UQSHL (register)
 2019-03-06 14:14:41 +00:00
Merry
948984bc94
Merge pull request #445 from lioncash/sqrt 
A64: Implement single and double-precision vector variant of FSQRT
 2019-03-06 14:14:21 +00:00
Merry
768a2a6973
Merge pull request #443 from lioncash/flag 
A64: Rearrange flag format/manipulation instructions
 2019-03-06 14:13:59 +00:00
Merry
a5ce4c7831
Merge pull request #441 from lioncash/constexpr 
common/bit_util: Mark a few functions as constexpr
 2019-03-05 19:57:12 +00:00
Merry
fa1671b655
Merge pull request #440 from lioncash/include 
common/fp: Remove unnecessary includes
 2019-03-05 19:56:58 +00:00
Merry
ecd544098b
Merge pull request #444 from lioncash/interpret 
A64: Fall back to interpreting for FCADD and FCMLA half-precision variants
 2019-03-05 18:51:50 +00:00
Lioncash
4429a0c8e5
A64: Implement UQSHL (register)'s scalar variant 
This can be implemented in terms of the vector variant.
 2019-03-04 14:26:25 -05:00
Lioncash
a3eeb334fa
A64: Implement SQSHL (register)'s scalar variant 
We can implement this in terms of the vector variant.
 2019-03-04 14:26:20 -05:00
Lioncash
16e6a8f343
A64: Implement single and double-precision vector variant of FSQRT 2019-03-04 13:37:27 -05:00
Lioncash
3e5a52cc66
frontend/ir: Add opcodes for vector square roots 2019-03-04 13:24:36 -05:00
Lioncash
d365d4083a
A64: Fall back to interpreting for FCADD and FCMLA half-precision variants 
Rather than straight-up treating them as undefined, we can fall back to an
interpreter in this case.
 2019-03-04 12:23:57 -05:00
Lioncash
36eba63641
A64: Rearrange flag format/manipulation instructions 
Gives these instructions better categorical labeling.
 2019-03-04 12:08:49 -05:00
Lioncash
9426cc9795
common/fp/op: Add FP conversion functions 2019-03-04 11:57:41 -05:00
Lioncash
7ae37bcc64
frontend/ir/microinstruction: Add missing cases for FPRecipExponent{32,64} for ReadsFromAndWritesToFPSRCumulativeExceptionBits() 
This was intended to be added within #437, but was missed
 2019-03-04 09:43:48 -05:00
Lioncash
e042c63de6
common/bit_util: Make a few functions as constexpr 
These four functions can be made constexpr with no issue.
 2019-03-04 09:21:29 -05:00
Lioncash
f01fca3bc3
common/fp: Remove unnecessary includes 2019-03-04 08:25:48 -05:00
Merry
f2fb7db668
Merge pull request #439 from lioncash/fcmla 
A64: Implement FCADD and FCMLA
 2019-03-03 14:43:22 +00:00
Merry
73e230aa3f
Merge pull request #438 from lioncash/fmulx 
A64: Implement scalar double/single precision FMULX (by element)
 2019-03-03 14:42:45 +00:00
Merry
456f2ec49f
Merge pull request #437 from lioncash/frecpx 
A64: Implement FRECPX (single, double precision)
 2019-03-03 14:42:23 +00:00
Merry
8be7648e79
Merge pull request #436 from lioncash/no-alloc 
A64: Implement LDNP/STNP
 2019-03-03 14:40:57 +00:00
Merry
4f88bf352f
Merge pull request #435 from lioncash/a32 
tests/a32/testenv: Make A32TestEnv's code_mem member a std::vector
 2019-03-03 12:59:36 +00:00
Merry
36fbe8de86
Merge pull request #434 from lioncash/format 
A32/translate_arm: Formatting/tidying up
 2019-03-03 12:58:03 +00:00
Lioncash
dae46f0132
A64: Implement FRECPX (single, double precision) 2019-03-02 23:31:30 -05:00
Lioncash
7b004e7230
frontend/ir/ir_emitter: Add opcodes for floating point reciprocal exponents 2019-03-02 23:31:30 -05:00
Lioncash
78742a6aea
common/fp/op: Add operations for floating-point reciprocal exponents 2019-03-02 23:31:26 -05:00
Lioncash
9f556b8447
A64: Implement FCMLA 2019-03-02 22:50:17 -05:00
Lioncash
0d9cca04c0
A64: Implement FCADD 2019-03-02 22:49:57 -05:00
Lioncash
ccc3d5258e
A64: Implement scalar double/single precision FMULX (by element) 2019-03-02 21:12:09 -05:00
Lioncash
fc111fda0c
A64: Implement LDNP/STNP 
LDNP and STNP indicate that a memory access is non-temporal/streaming
(i.e. unlikely to be repeated), allowing data caching to not be
performed. However, given this is only a hint, we can treat these two
instructions as regular LDP and STP instructions for the time being.
 2019-03-02 17:41:09 -05:00
Lioncash
5c11851f33
tests/a32/testenv: Make A32TestEnv's code_mem member a std::vector 
Makes the data member consistent with the A64 test environment.
 2019-03-02 16:26:37 -05:00
Merry
48cc7274c1
Merge pull request #433 from lioncash/unicorn 
tests/unicorn_emu: Add getters and setters for PC/SP
 2019-03-01 22:03:20 +00:00
Merry
468aba4ccd
Merge pull request #432 from lioncash/catch 
externals: Update Catch to 2.6.1
 2019-03-01 21:58:06 +00:00
Merry
8f4ea28988
Merge pull request #431 from lioncash/noexcept 
backend/x64/a32_interface: Mark Context move constructor and move assignment as noexcept
 2019-03-01 21:57:48 +00:00
Lioncash
02a70f3be1
translate_arm/coprocessor: Minor tidying up 2019-03-01 03:15:43 -05:00
Lioncash
c1f4241ca8
translate_arm/vfp2: Invert conditionals where applicable 2019-03-01 03:10:18 -05:00
Lioncash
797fca0125
translate_arm/synchronization: Invert conditionals where applicable 2019-03-01 02:23:24 -05:00
Lioncash
6a851dc412
translate_arm/status_register_access: Invert conditionals where applicable 2019-03-01 02:11:05 -05:00
Lioncash
18276e7c66
translate_arm/saturated: Invert conditionals where applicable 2019-03-01 02:05:30 -05:00
Lioncash
55fff7b2f6
translate_arm/reversal: Invert conditionals where applicable 2019-03-01 01:51:47 -05:00