SachinVin
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8781a0f184
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backend\A64\emit_a64_data_processing.cpp:Implement ops
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2020-05-23 19:54:39 +05:30 |
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SachinVin
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a66bcdfc91
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backend\A64\emit_a64_data_processing.cpp: Mostly empty file
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2020-05-23 19:54:39 +05:30 |
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SachinVin
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9df55fc951
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backend/a64: Add a32_interface
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2020-05-23 19:54:38 +05:30 |
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SachinVin
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cb56c74d19
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backend/a64: Port a32_emit_a64
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2020-05-23 19:54:38 +05:30 |
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SachinVin
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4b48391fd3
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backend/a64: Port block_of_code and emit_a64
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2020-05-23 19:54:38 +05:30 |
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SachinVin
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0708019057
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backend/a64: Port callback functions
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2020-05-23 19:54:37 +05:30 |
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SachinVin
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f3bb2e5f92
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backend/a64: Port exception handler
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2020-05-23 19:54:37 +05:30 |
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SachinVin
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0d6b748b2a
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backend/a64: Port const pool
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2020-05-23 19:54:37 +05:30 |
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SachinVin
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5c9179e2db
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backend/a64: Port reg_alloc
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2020-05-23 19:54:36 +05:30 |
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SachinVin
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a37f9c4cc6
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backend/a64: Port ABI functions
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2020-05-23 19:54:36 +05:30 |
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SachinVin
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ab07872025
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backend/a64: Port perfmap
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2020-05-23 19:54:36 +05:30 |
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SachinVin
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be80e558c9
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backend/a64: Port hostloc
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2020-05-23 19:54:36 +05:30 |
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SachinVin
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9ca0155c19
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backend/a64: Devirtualize functions for a64
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2020-05-23 19:54:35 +05:30 |
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SachinVin
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fbb03a2a1b
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backend/a64: Port block_range_info
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2020-05-23 19:54:35 +05:30 |
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SachinVin
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19b7fba235
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CMakeModules\DetectArchitecture.cmake: Refactor ARCHITECTURE to DYNARMIC_ARCHITECTURE
Don't rely on super-project's definition of ARCHITECTURE
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2020-05-23 19:54:35 +05:30 |
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SachinVin
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9bcbdacd2b
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[HACK] A32/exception_generating: Interpret undefined instructions
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2020-05-23 19:54:35 +05:30 |
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SachinVin
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c72550f7d9
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[HACK] CMakeLists: Do not build A64 tests on AArch64
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2020-05-23 19:54:34 +05:30 |
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MerryMage
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8fdeb84822
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fuzz_thumb: Add [JitA64] tag to supported instructions
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2020-05-23 19:54:34 +05:30 |
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SachinVin
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4e4f2b8ef0
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backend/A64: Port a32_jitstate
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2020-05-23 19:54:34 +05:30 |
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MerryMage
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8de86b391f
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code_block: Support Windows and fix munmap check
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2020-05-23 19:54:33 +05:30 |
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SachinVin
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0a55e1b11e
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ir_opt: Port a32_merge_interpreter_blocks
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2020-05-23 19:54:33 +05:30 |
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SachinVin
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f654dbb29b
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assert: Use __android_log_print on Android
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2020-05-23 19:54:33 +05:30 |
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SachinVin
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668d20391a
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CMakeLists: xbyak should only be linked on x64
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2020-05-23 19:54:32 +05:30 |
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SachinVin
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0ce4fa4480
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a64_emitter: Fix ABI push and pop
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2020-05-23 19:54:32 +05:30 |
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SachinVin
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ddc8b7f932
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a64_emitter: More style cleanup
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2020-05-23 19:54:32 +05:30 |
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SachinVin
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6010c48bd0
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a64_emitter: Style cleanup
|
2020-05-23 19:54:31 +05:30 |
|
BreadFish64
|
b8369d77ac
|
Backend/A64: add jitstate_info.h
|
2020-05-23 19:54:31 +05:30 |
|
BreadFish64
|
7905eeb94b
|
Backend/A64: Add Dolphin's ARM emitter
|
2020-05-23 19:54:31 +05:30 |
|
BreadFish64
|
f7664d9161
|
Add aarch64 CI
|
2020-05-23 19:54:31 +05:30 |
|
Lioncash
|
659d78c9c4
|
A32: Implement ASIMD VSWP
A trivial one to implement, this just swaps the contents of two
registers in place.
|
2020-05-22 19:43:24 +01:00 |
|
MerryMage
|
d0d50c4824
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print_info: Use VFP and ASIMD decoders to get dynarmic name for instruction
|
2020-05-17 22:48:14 +01:00 |
|
MerryMage
|
d0075f4ea6
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print_info: Use LLVM to disassemble A32
|
2020-05-17 22:30:46 +01:00 |
|
MerryMage
|
c59a127e86
|
opcodes: Switch from std::map to std::array
Optimization.
|
2020-05-17 17:01:39 +01:00 |
|
MerryMage
|
d0b45f6150
|
A32: Implement ARMv8 VST{1-4} (multiple)
|
2020-05-17 17:01:39 +01:00 |
|
Lioncash
|
eb332b3836
|
asimd_three_same: Unify BitwiseInstructionWithDst with BitwiseInstruction
Now that all bitwise instructions are implemented, we can unify all of
them together using if constexpr.
|
2020-05-16 20:22:12 +01:00 |
|
Lioncash
|
f42b3ad4a0
|
A32: Implement ASIMD VBIF (register)
|
2020-05-16 20:22:12 +01:00 |
|
Lioncash
|
ee9a81dcba
|
A32: Implement ASIMD VBIT (register)
|
2020-05-16 20:22:12 +01:00 |
|
Lioncash
|
d624059ead
|
A32: Implement ASIMD VBSL (register)
|
2020-05-16 20:22:12 +01:00 |
|
Lioncash
|
66663cf8e7
|
asimd_three_same: Collapse all bitwise implementations into a single code path
Less code and results in only writing the parts that matter once.
|
2020-05-16 20:22:12 +01:00 |
|
Lioncash
|
4b5e3437cf
|
A32: Implement ASIMD VEOR (register)
|
2020-05-16 20:22:12 +01:00 |
|
Lioncash
|
67b284f6fa
|
A32: Implement ASIMD VORN (register)
|
2020-05-16 20:22:12 +01:00 |
|
Lioncash
|
1fdd90ca2a
|
A32: Implement ASIMD VORR (register)
|
2020-05-16 20:22:12 +01:00 |
|
Lioncash
|
9b93a9de46
|
a32_jitstate: Remove obsoleted debug assert
|
2020-05-16 20:22:12 +01:00 |
|
Lioncash
|
64fa804dd4
|
A32: Implement ASIMD VBIC (register)
|
2020-05-16 20:22:12 +01:00 |
|
Lioncash
|
0441ab81a1
|
A32: Implement ASIMD VAND (register)
|
2020-05-16 20:22:12 +01:00 |
|
Lioncash
|
1b25e867ae
|
asimd_load_store_structures: Simplify ToExtRegD()
ExtReg has a supplied operator+, so we can make use of that instead.
|
2020-05-16 11:27:22 -04:00 |
|
MerryMage
|
2169653c50
|
a64_emit_x64: Invalid regalloc code for EmitA64ExclusiveReadMemory128
Attempted to allocate args[0] after end of allocation scope
|
2020-05-16 14:11:23 +01:00 |
|
MerryMage
|
1a0bc5ba91
|
A32/ASIMD: ARMv8: Implement VLD{1-4} (multiple)
|
2020-05-16 14:11:23 +01:00 |
|
MerryMage
|
e7f1a0d408
|
A32: ARMv8: Implement LDA{,EX}{,B,D,H} and STL{,EX}{,B,D,H}
|
2020-05-15 21:07:36 +01:00 |
|
Lioncash
|
8808b8c479
|
cpu_info: Make test non-allocating
Same behavior, but makes it non-allocating by using a constexpr
std::array instead of a std::vector.
|
2020-05-12 09:52:55 +01:00 |
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