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Author SHA1 Message Date
MerryMage
86cd8c9a69 tests: Add print_info program 
Eases debugging by printing out dynarmic IR for a given A64 instruction, along with
information about what instruction dynarmic thinks it is.

Also prints an LLVM disassembly of the instruction.
 2018-06-27 21:23:14 +01:00
MerryMage
f4e824d396 ir/basic_block: Add missing U16 immediate type to DumpBlock 2018-06-27 21:23:05 +01:00
MerryMage
89a2b80c1f llvm_disassemble: Allow disassembly of invalid AArch64 instructions 2018-06-27 21:22:53 +01:00
Lioncash
11941f70e1 externals: Update catch to v2.2.3 
Keeps the unit-testing library up to date.
 2018-06-09 22:33:57 +01:00
Lioncash
96c4b1e793 A64: Implement FABD's scalar single/double precision variant 2018-06-09 10:28:45 +01:00
Lioncash
2b0df59e7b A64: Implement FABD's vector single/double precision variant 2018-06-09 10:28:45 +01:00
Lioncash
cfeda05286 ir: Add opcode for performing FP vector absolute differences 2018-06-09 10:28:45 +01:00
MerryMage
c15c9e7049 A64: Implement FNMSUB 2018-06-08 15:23:44 +01:00
MerryMage
6ad682c1c4 A64: Implement FNMADD 2018-06-08 15:23:42 +01:00
MerryMage
a0093c031f A64: Implement FMSUB 2018-06-08 15:23:40 +01:00
MerryMage
4a2c374500 A64: Implement FMADD 2018-06-08 15:23:37 +01:00
MerryMage
f05cb06244 IR: Implement FPMulAdd 2018-06-08 15:23:35 +01:00
Lioncash
0299f05698 A64: Implement FCMGT, FCMGE (register) vector double and single precision variants 2018-06-05 17:21:35 +01:00
Lioncash
7454c8a93a A64: Implement FCMGT, FCMGE, FCMLE, FCMLT (zero) vector double and single precision variants. 2018-06-05 17:21:35 +01:00
Lioncash
21a38854e5 ir: Add opcode for floating-point GE and GT comparisons 
The rest of the comparisons can be implemented in terms of these two
 2018-06-05 17:21:35 +01:00
Lioncash
9d27e78989 A64: Implement FCMEQ (zero)'s vector single and double precision variant 2018-06-03 21:49:06 +01:00
Lioncash
0ca366b94e A64: Implement FCMEQ (register)'s vector single and double precision variant 2018-06-03 21:49:06 +01:00
Lioncash
239d2243c0 ir: Add opcodes for floating-point vector equalities 2018-06-03 21:49:06 +01:00
Lioncash
7dc6b5abb3 fuzz_with_unicorn: Make float_numbers in floating-point tests constexpr 
Given this is just a lookup table, this can be made immutable.
 2018-06-02 16:47:13 +01:00
Lioncash
06c1cf6721 emit_x64_vector: Vectorize fallback case in EmitVectorMultiply64() 
Gets rid of the need to perform a fallback.
 2018-05-26 21:33:46 +01:00
Lioncash
b747b67354 emit_x64_vector: Add break to final case in EmitVectorRoundingHalvingAddUnsigned() 
This doesn't alter behavior but does make the code better if anything
else is ever added to this function in the future.
 2018-05-26 21:25:14 +01:00
Lioncash
c623a94a4d A64: Implement SRHADD and URHADD 2018-05-26 11:48:56 +01:00
Lioncash
2652e92928 ir: Add opcodes for performing rounding halving adds 2018-05-26 11:48:56 +01:00
Lioncash
990a569b7a emit_x64_vector: Simplify AVX-512 codepath in EmitVectorMultiply64 
I realized I introduced a helper for simple AVX operation emitting, so
use that instead of writing it all out long-form.
 2018-05-23 08:02:12 +01:00
Lioncash
66c5d8fb06 A64: Implement UMLAL{2}, UMLSL{2}, and UMULL{2} 
Now that we have the helper function set up for the signed variants, we
can also modify it to be used with the unigned ones by performing a zero
extension instead of a sign extension.
 2018-05-23 07:58:41 +01:00
Lioncash
5f53fd2be8 A64: Implement SMLSL{2} 2018-05-23 07:58:41 +01:00
Lioncash
b6ed3f9c66 A64: Implement SMLAL{2} 2018-05-23 07:58:41 +01:00
Lioncash
2bfe1ce838 A64: Implement SMULL{2} 2018-05-23 07:58:41 +01:00
Lioncash
be453b0e1c fuzz_with_unicorn: Remove exclusion of FMOV (imm) for FP-16 floats 
Qemu, or rather, Unicorn now supports FP-16, since I backported support
for the recent changes to mainline Qemu relating to FP-16 support.
 2018-05-19 12:25:43 +01:00
Lioncash
1f00e53b54 A64: Implement SABAL/SABAL2 and SABDL/SABDL2 
Now that we have a helper function for the unsigned variants, we can
modify it to also be usable with the signed variants.
 2018-05-14 23:10:01 +01:00
Lioncash
de3b545e57 A64: Implement UABAL/UABAL2 2018-05-14 23:10:01 +01:00
Lioncash
e1ab52c057 A64: Implement UABDL/UABDL2 2018-05-14 23:10:01 +01:00
Lioncash
7cd0ff18bf emit_x64_vector: Emit VPMULLQ in EmitVectorMultiply64 on AVX-512{DQ, VL} capable CPUs 
Shortens code-gen down to a single instruction in the 64-bit path.
 2018-05-14 23:09:31 +01:00
Lioncash
f8f4f9abb4 A64: Implement LDR (literal, SIMD&FP) 2018-05-14 23:09:15 +01:00
Lioncash
b00f6d1044 Correct typo in DataCacheOperation enum 
Fixes a typo for the InvalidateByVAToPoC enum entry. Given yuzu is the
only known user of 64-bit mode and it doesn't use this value, we can get
away with changing this.
 2018-05-14 15:39:08 +01:00
Lioncash
ced64f7dda A64: Implement FABS' half-precision variant 2018-05-12 11:17:46 +01:00
Lioncash
672641de2c A64: Implement FABS' single and double precision variant 2018-05-12 11:17:46 +01:00
Lioncash
34e1b030dd A64: Implement URSHR (scalar) and URSRA (scalar) 
Now that the utility function is all set up from implementing SRSRA, the
unsigned variants can now be trivially implemented by modifying the
utility function to perform a logical shift right instead of an
arithmetical shift right for the unsigned case.
 2018-05-12 11:17:19 +01:00
Lioncash
e662942ee3 A64: Implement SRSRA (scalar) 2018-05-12 11:17:19 +01:00
Lioncash
4a81075641 A64: Implement SRSHR (scalar) 2018-05-12 11:17:19 +01:00
Lioncash
ae666903c4 A64: Implement SABA 2018-05-12 11:16:42 +01:00
Lioncash
1629beed25 A64: Implement SABD 2018-05-12 11:16:42 +01:00
Lioncash
d7951233bd ir: Add opcodes for signed absolute differences 2018-05-12 11:16:42 +01:00
Tillmann Karras
0718ee4482 decoder_detail: use structured bindings 2018-05-12 11:15:39 +01:00
Lioncash
cee8bfa797 CMakeLists: Add detection for Aarch64 compiler environments 
Just closes a small hole in architecture detection for the ARM family.
 2018-05-10 00:35:50 +01:00
Lioncash
e0faf3277e simd_two_register_misc: Handle 64-bit case for SCVTF_int_4 2018-05-08 18:14:50 +01:00
Lioncash
b166981ff5 ir: Add opcode to perform the vector conversion S64->F64 
Unfortunately x86 prior to AVX-512 doesn't really give us any convenient instruction to do the work for us
 2018-05-08 18:14:50 +01:00
Lioncash
4d2c5184ff A64: Implement SHLL/SHLL2 2018-05-08 17:57:55 +01:00
Lioncash
ae57f6eb58 A64: Add missing decoding for PRFM (unscaled offset) 2018-05-08 15:01:53 +01:00
Lioncash
3e0861d013 A64: Implement UHSUB 2018-05-07 19:04:10 +01:00