MerryMage
f626ff82d0
backend_x64: Fix FPVectorMulAdd and FPMulAdd NaN handling with denormals
...
Denormals should be treated as zero in NaN handler
2018-07-31 16:07:46 +01:00
MerryMage
adeb9d9ba0
a32/fuzz_arm: Disable vfp tests
2018-07-31 16:01:28 +01:00
MerryMage
19ea70d3a0
fuzz_with_unicorn: Randomize FPCR.FZ
2018-07-31 15:39:39 +01:00
MerryMage
895db36543
backend_x64: Fix bugs when FPCR.FZ=1
...
Bugs:
* DenormalsAreZero flushed to positive zero instead of preserving sign.
* FMAXNM/FMINNM (scalar) should perform DAZ *before* special zero handling.
* FMAX/FMIN/FMAXNM/FMINNM (vector) did not DAZ.
2018-07-31 15:39:33 +01:00
MerryMage
d7e2de2659
fuzz_with_unicorn: Extract RandomFpcr function
...
Deduplicate randomization of fpcr and make use of FP::FPCR
2018-07-31 12:35:04 +01:00
MerryMage
c858d6c7b4
fp/info: Deduplicate functions
2018-07-30 20:25:29 +01:00
MerryMage
5b88ec252c
emit_x64_floating_point: Deduplicate EmitFPMulAdd implementation
2018-07-30 20:16:45 +01:00
MerryMage
73d3efc3e0
emit_x64_floating_point: Deduplicate code
2018-07-30 15:13:43 +01:00
MerryMage
c9508c3d13
fuzz_with_unicorn: Randomize FPCR.DN
2018-07-30 14:52:22 +01:00
MerryMage
29708331bb
emit_x64_vector_floating_point: Fix FPVector{Max,Min} when FPCR.DN = 1
2018-07-30 14:52:22 +01:00
MerryMage
150764f718
emit_x64_floating_point: Fix FP{Max,Min} when FPCR.DN = 1
2018-07-30 14:52:22 +01:00
MerryMage
b7d209cfa4
IR: SSE4.1 implementation of FPVectorRoundInt
2018-07-30 14:52:22 +01:00
MerryMage
8cf8270139
A64: Implement FRINT{N,M,P,Z,A,X,I} (vector), single/double variant
2018-07-30 13:32:20 +01:00
MerryMage
8f46c26d26
IR: Initial implementation of FPVectorRoundInt
2018-07-30 13:31:51 +01:00
MerryMage
97017bbdf7
A64: Implement SQADD and SQSUB, scalar variant
2018-07-30 11:01:38 +01:00
MerryMage
ce58863903
IR: Generalise SignedSaturated{Add,Sub} to support more bitwidths
2018-07-30 11:01:36 +01:00
MerryMage
e80f8ff244
a64_emit_x64: Bugfix EmitA64OrQC - Incorrect argument
2018-07-30 11:00:37 +01:00
Lioncash
1e4ec7e1f0
simd_three_same: Extract non-paired SMAX, SMIN, UMAX, UMIN code to a common function
...
Deduplicates a bit of code and makes its layout consistent with the
paired variants
2018-07-30 08:40:32 +01:00
Lioncash
6f9dc9b143
A64: Implement SMAXP, SMINP, UMAXP, UMINP
2018-07-30 08:40:32 +01:00
Lioncash
1dfb29fc14
ir: Add opcodes for vector paired maximum and minimums
...
For the time being, we can just do a naive implementation which avoids
falling back to the interpreter a bit. Horizontal operations aren't
necessarily x86 SIMD's forte anyways.
2018-07-30 08:40:32 +01:00
Lioncash
017b51095f
A64: Implement SMAXV, SMINV, UMAXV, and UMINV
2018-07-30 08:39:33 +01:00
Lioncash
aae22eec26
ir: Add opcodes for performing scalar integral min/max
2018-07-30 08:39:33 +01:00
Lioncash
6ef3af3bc9
A64: Implement PMULL{2}
2018-07-29 10:04:58 +01:00
Lioncash
2a4ce19af3
translate: Deduplicate GetDataSize() functions
...
Avoids defining the same function multiple times in different files.
2018-07-29 10:00:34 +01:00
Lioncash
0e015008af
floating_point_{conditional}_compare: Deduplicate code
...
Deduplicates the implementation code of instructions by extracting the
code to a common function.
2018-07-29 10:00:34 +01:00
MerryMage
259237ce58
common: Move all cryptographic function to common/crypto
2018-07-29 08:49:12 +01:00
MerryMage
c5f1080b40
a32_emit_x64: BMI2 implementation of A32SetCpsr
2018-07-27 11:41:31 +01:00
MerryMage
a23304a16c
a32_emit_x64: Shorten EmitA32GetCpsr
2018-07-27 11:24:06 +01:00
MerryMage
57604d2ea8
a32_emit_x64: Assert that memory layout assumption in EmitA32GetCpsr is valid
2018-07-26 19:26:01 +01:00
Lioncash
945fa48667
A64: Implement PMUL
2018-07-26 16:16:30 +01:00
Lioncash
656a4042a2
ir: Add opcode for performing polynomial multiplication
2018-07-26 16:16:30 +01:00
MerryMage
05143df9d8
A64: Implement FCVT{N,M,A,P}{U,S} (vector), FCVTZU (vector, integer), single/double variant
2018-07-26 12:48:36 +01:00
MerryMage
34ce767a00
A64: Implement FCVTZS (vector, integer), single/double variant
2018-07-26 12:48:36 +01:00
MerryMage
0f9bc2d391
IR: Implement FPVectorTo{Signed,Unsigned}Fixed
2018-07-26 12:48:36 +01:00
MerryMage
0189e4454a
fp/info: Replace constant value generators with FPValue
...
Instead of having multiple different functions we can just have one.
2018-07-26 11:35:35 +01:00
MerryMage
db165684c0
emit_x64_vector_floating_point: AVX implementation of FPVector{Max,Min}
2018-07-26 10:10:47 +01:00
MerryMage
31148bdb42
emit_x64_vector_floating_point: Remove unnecessary double jump in HandleNaNs
2018-07-26 09:42:34 +01:00
Lioncash
4c3ca51e86
A64: Implement FMAX's vector single and double precision variants
2018-07-26 09:32:02 +01:00
Lioncash
bf0f21cc12
A64: Implement FMIN's vector single and double precision variants
2018-07-26 09:32:02 +01:00
MerryMage
76f0ca04d6
IR: Implement FPVector{Max,Min}
2018-07-26 09:31:56 +01:00
MerryMage
6c37c311de
FPRecipEstimate: Move offset out of function
...
MSVC has weird lambda capturing rules.
2018-07-25 19:22:35 +01:00
MerryMage
59546f3c60
microinstruction: Update ReadsFromAndWritesToFPSRCumulativeExceptionBits
2018-07-25 19:17:07 +01:00
MerryMage
3f6b03a06b
A64: Implement FRECPS, vector/scalar single/double variants
2018-07-25 19:14:23 +01:00
MerryMage
2d2ca5ebc1
IR: Implement FPRecipStepFused, FPVectorRecipStepFused
2018-07-25 19:14:23 +01:00
MerryMage
5cb9f1dab2
A64: Implement FRECPE, vector single/double variant
2018-07-25 18:55:58 +01:00
MerryMage
c5a14ab21b
IR: Implement FPVectorRecipEstimate
2018-07-25 18:55:40 +01:00
MerryMage
56f8a0b172
A64: Implement FRECPE, scalar single/double variant
2018-07-25 18:47:45 +01:00
MerryMage
fde69b4d36
IR: Implement FPRecipEstimate
2018-07-25 18:47:22 +01:00
MerryMage
186e52ca50
IR: Implement FPRecipEstimate
2018-07-25 18:36:40 +01:00
MerryMage
cf2e1aed96
fp: Change FPUnpacked to a normalized representation
...
Having a known position for the highest set bit makes writing algorithms easier
2018-07-25 17:42:36 +01:00
