Citra-emu/dynarmic
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Author SHA1 Message Date
BreadFish64
af010996a5 backend/A64: fix mp 2020-11-22 17:31:39 -05:00
SachinVin
d472e5ba61 backend/A64: Move SP to FP in GenMemoryAccessors + Minor cleanup and 2020-11-22 17:31:39 -05:00
SachinVin
8e1f543bfb backend/A64: Use X26 for storing remaining cycles. 2020-11-22 17:31:39 -05:00
BreadFish64
ec293f447b backend/A64: add fastmem support 
fix crash on game close

fix generic exception handler

reorder hostloc gpr list

use temp register instead of X0 for writes

go back to regular std::partition
 2020-11-22 17:31:39 -05:00
BreadFish64
0aa938209c merge fastmem 2020-11-22 17:31:39 -05:00
SachinVin
1234add918 backend\A64\constant_pool.cpp: Correct offset calculation 2020-11-22 17:31:39 -05:00
SachinVin
b4239a6a06 backend/A64/a32_jitstate: Upstream changes from x64 backend 2020-11-22 17:31:38 -05:00
SachinVin
85b607bdaa backend/A64: Add test for q flag being incorrectly set 2020-11-22 17:31:38 -05:00
SachinVin
35e40cb1a9 backend/A64/a32_emit_a64.cpp: Use unused HostCall registers 2020-11-22 17:30:50 -05:00
SachinVin
45b8f69855 backend/A64/a32_emit_a64.cpp: Use MOVP2R instead of MOVI2R. 2020-11-22 17:30:50 -05:00
SachinVin
9da0572c0d backend/A64/abi: Fix FP caller and callee save registers 2020-11-22 17:30:50 -05:00
SachinVin
2752b9c4e5 a64/block_of_code: use GetWritableCodePtr() instead of const_cast<...>(GetCodePtr()) 2020-11-22 17:30:50 -05:00
SachinVin
481af9f823 backend/A64/constant_pool: Clean up unused stuff 2020-11-22 17:30:50 -05:00
SachinVin
f837fab9dd emit_a64_data_processing.cpp: remove pointless DoNZCV. 2020-11-22 17:30:50 -05:00
SachinVin
50bf478e6a IR + backend/*: add SetCpsrNZCVRaw and change arg1 type of SetCpsrNZCV to IR::NZCV 2020-11-22 17:30:50 -05:00
SachinVin
16dbb68715 backend/A64: Fix ASR impl 2020-11-22 17:30:50 -05:00
SachinVin
f02ef43aa8 a64_emitter: Use Correct alias for ZR and WZR in CMP 2020-11-22 17:30:50 -05:00
SachinVin
0f3ef9babe backend/A64: Use CSLE instead of branches for LSL LSR and ASR + minor cleanup 2020-11-22 17:30:50 -05:00
SachinVin
f661d13906 backend/A64: Use correct register size for EmitNot64 2020-11-22 17:30:50 -05:00
SachinVin
b4addd2564 tests/A32: Check if Q flag is cleared properly 2020-11-22 17:30:49 -05:00
SachinVin
7c7968741e backend/A64: SignedSaturatedSub and SignedSaturatedAdd 2020-11-22 17:30:23 -05:00
SachinVin
131f9d69bd backend/A64/emit_a64_saturation.cpp: Implement EmitSignedSaturation and EmitUnsignedSaturation 
Implements SSAT SSAT16 USAT USAT16 QASX QSAX UQASX UQSAX
 2020-11-22 17:30:23 -05:00
SachinVin
5d0f1e84e8 backend/A64: add emit_a64_saturation.cpp 2020-11-22 17:30:23 -05:00
SachinVin
6cc068b8b9 backend/A64: Fix EmitA32SetCpsr 2020-11-22 17:30:23 -05:00
SachinVin
dbc7562190 backend/A64/devirtualize: remove unused DevirtualizeItanium 2020-11-22 17:30:23 -05:00
SachinVin
035dd1d2e0 backend/A64: refactor to fpscr from mxcsr 2020-11-22 17:30:23 -05:00
SachinVin
07922b318d backend/A64: Use ScratchGpr() instead of ABI_SCRATCH1 where possible 2020-11-22 17:30:23 -05:00
SachinVin
6d36c1f4f9 backend/A64: support for always_little_endian 2020-11-22 17:30:23 -05:00
SachinVin
287658878d backend/a64: Add hook_hint_instructions option 
534eb0f
 2020-11-22 17:30:23 -05:00
SachinVin
ccf47ec5cd backend /A64: cleanup 2020-11-22 17:30:23 -05:00
SachinVin
428477abe1 gitignore: add .vs dir 2020-11-22 17:30:23 -05:00
SachinVin
918be1fe40 Minor style fix 2020-11-22 17:30:23 -05:00
SachinVin
90b1e62490 backend\A64\emit_a64_packed.cpp: Implement AddSub halving and non halving 2020-11-22 17:30:23 -05:00
SachinVin
8245465b98 backend\A64: Instructions that got implemented on the way 2020-11-22 17:30:23 -05:00
SachinVin
f56f9c2b29 backend\A64\emit_a64_packed.cpp: Implement Unsigned Sum of Absolute Differences 2020-11-22 17:30:23 -05:00
SachinVin
5958810e56 a64 emitter: Absolute Difference and add across vector instructions 2020-11-22 17:30:23 -05:00
SachinVin
ab27fbc0c6 backend\A64\emit_a64_packed.cpp: Implement Packed Select 2020-11-22 17:30:23 -05:00
SachinVin
01682cd735 Backend/a64: Fix asset when falling back to interpreter 2020-11-22 17:30:23 -05:00
SachinVin
2c2666b0eb backend\A64\emit_a64_packed.cpp: Implement Packed Halving Add/Sub instructions 2020-11-22 17:30:23 -05:00
SachinVin
758481f5db backend\A64\emit_a64_packed.cpp: Implement Packed Saturating instructions 2020-11-22 17:30:23 -05:00
SachinVin
c8a910a009 backend\A64\emit_a64_packed.cpp: Implement SignedPacked*- ADD and SUB 2020-11-22 17:30:23 -05:00
SachinVin
2a378692fa a64 emitter: Vector Halving and Saturation instructions 2020-11-22 17:30:23 -05:00
SachinVin
a698e35422 backend\A64\emit_a64_packed.cpp: Implement UnsignedPacked*- ADD and SUB... 
with few other in the emitter
 2020-11-22 17:30:23 -05:00
SachinVin
7b6cc4ec70 a64 emitter: fix Scalar Saturating Instructions 2020-11-22 17:30:23 -05:00
SachinVin
1a03e361c3 A64 Emitter: Implement Saturating Add and Sub 2020-11-22 17:30:23 -05:00
SachinVin
2f9f317c9e backend\A64\emit_a64_data_processing.cpp: Implement Division 2020-11-22 17:30:23 -05:00
SachinVin
374c703335 backend\A64\emit_a64_data_processing.cpp: Implement 64bit CLZ 2020-11-22 17:30:23 -05:00
SachinVin
78619e5620 backend\A64\emit_a64_data_processing.cpp: Implement 64bit LSL and ROR Instructions 
Also EmitTestBit
 2020-11-22 17:30:23 -05:00
SachinVin
0398fc9b41 backend\A64\emit_a64_data_processing.cpp: Implement 64bit Logical Instructions 2020-11-22 17:30:23 -05:00
SachinVin
08ada2919d backend/a64: implememnt CheckBit 2020-11-22 17:30:23 -05:00