SachinVin
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5958810e56
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a64 emitter: Absolute Difference and add across vector instructions
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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ab27fbc0c6
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backend\A64\emit_a64_packed.cpp: Implement Packed Select
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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01682cd735
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Backend/a64: Fix asset when falling back to interpreter
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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2c2666b0eb
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backend\A64\emit_a64_packed.cpp: Implement Packed Halving Add/Sub instructions
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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758481f5db
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backend\A64\emit_a64_packed.cpp: Implement Packed Saturating instructions
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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c8a910a009
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backend\A64\emit_a64_packed.cpp: Implement SignedPacked*- ADD and SUB
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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2a378692fa
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a64 emitter: Vector Halving and Saturation instructions
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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a698e35422
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backend\A64\emit_a64_packed.cpp: Implement UnsignedPacked*- ADD and SUB...
with few other in the emitter
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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7b6cc4ec70
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a64 emitter: fix Scalar Saturating Instructions
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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1a03e361c3
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A64 Emitter: Implement Saturating Add and Sub
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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2f9f317c9e
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backend\A64\emit_a64_data_processing.cpp: Implement Division
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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374c703335
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backend\A64\emit_a64_data_processing.cpp: Implement 64bit CLZ
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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78619e5620
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backend\A64\emit_a64_data_processing.cpp: Implement 64bit LSL and ROR Instructions
Also EmitTestBit
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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0398fc9b41
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backend\A64\emit_a64_data_processing.cpp: Implement 64bit Logical Instructions
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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08ada2919d
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backend/a64: implememnt CheckBit
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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263a7c823a
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backend/a64: Redesign Const Pool
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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cb7228828e
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backend\A64\emit_a64_floating_point.cpp: Fix include paths
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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fe63ef0486
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backend\A64\a32_emit_a64.cpp: Fix Coproc* after rebase
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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5bf010cc62
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backend/a64/opcodes.inc: Coproc instructions
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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99728efc1b
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a64 emitter: Fix LDR literal
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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c45d11e0af
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a64 emitter: Move IsInRange* and MaskImm* into anon namespace
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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157435bd07
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backend\A64\emit_a64_floating_point.cpp: Implement VADD VSUB VMUL and other stuff
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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7bae3c14ba
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backend\A64\emit_a64_floating_point.cpp: Implement VABS VNEG VCMP and a few others
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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b491d1aae6
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frontend/A32/Decoder : (backend/a64)VMOV
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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0784f2fe0d
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backend\A64\emit_a64_floating_point.cpp: Implement VCVT instructions
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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b61bb8e313
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backend\A64\emit_a64_floating_point.cpp: part 1
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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25532e4999
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backend/a64/reg_alloc: Fix EmitMove for FPRs
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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c1130497b1
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A64 emitter: Support for 64bit FMOV
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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c4fb80bf05
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a64 backend: Load "guest_FPSR"
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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83ef2b7070
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A64 backend: Add Get/SetExtendedRegister and Get/SetGEFlags
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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eacc261010
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tests: Dont compile A64 tests for non x64 backend
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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89bb32bed5
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travis a64: unicorn
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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20ab2e2e80
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travis a64 backend
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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3850598ca2
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Frontend/A32: a64 backend; Interpret SEL
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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80a67a8f31
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frontend/A32: A64 Backend implemented instructions
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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0deeb504b6
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backend\A64\emit_a64_data_processing.cpp: Implement REV and CLZ ops
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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0b9008680a
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backend\A64\emit_a64_data_processing.cpp: Implement Sext an Zext ops
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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71bf3432a0
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backend\A64\emit_a64_data_processing.cpp: Implement Logical ops
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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ea54d71e3b
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backend\A64\emit_a64_data_processing.cpp: Implement Arithmetic ops
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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361d221741
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backend\A64\emit_a64_data_processing.cpp: Implement Shift and Rotate ops
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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85fa3096dd
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backend\A64\emit_a64_data_processing.cpp:Implement ops
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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ddf33c425b
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backend\A64\emit_a64_data_processing.cpp: Mostly empty file
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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3119f62f24
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backend/a64: Add a32_interface
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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454aee658f
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backend/a64: Port a32_emit_a64
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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cc83d2344e
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backend/a64: Port block_of_code and emit_a64
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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4edf81f785
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backend/a64: Port callback functions
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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ea221bcc94
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backend/a64: Port exception handler
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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598392c9f6
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backend/a64: Port const pool
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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800d1e34e2
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backend/a64: Port reg_alloc
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2020-11-22 17:30:23 -05:00 |
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SachinVin
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2645f51713
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backend/a64: Port ABI functions
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2020-11-22 17:30:23 -05:00 |
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